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1/110 june 2004 psd813f1v flash in-system programmable (isp) peripherals for 8-bit mcus, 3.3v features summary dual bank flash memories ? 1 mbit of primary flash memory (8 uniform sectors) ? 256 kbit secondary eeprom (4 uniform sectors) ? concurrent operation: read from one memory while erasing and writing the other 16 kbit sram (battery-backed) pld with macrocells ? over 3,000 gates of pld: dpld and cpld ? dpld - user-defined internal chip-select decoding ? cpld with 16 output macrocells (omcs) and 24 input macrocells (imcs) 27 reconfigurable i/os ? 27 individually configurable i/o port pins that can be used for the following functions: mcu i/os; pld i/os; latched mcu address output; and special function i/os. note: 16 of the i/o ports may be configured as open-drain outputs. enhanced jtag serial port ? built-in jtag-compliant serial port allows full-chip in-system programmability (isp) ? efficient manufacturing allows for easy product testing and programming page register ? internal page register that can be used to expand the microcontroller address space by a factor of 256. programmable power management figure 1. packages high endurance: ? 100,000 erase/write cycles of flash memory ? 10,000 erase/write cycles of eeprom ? 1,000 erase/write cycles of pld ? data retention: 15-year minimum at 90c (for main flash, boot, pld and configuration bits). single supply voltage: ? 3.3v10% for psd813f1v standby current as low as 50a pqfp52 (m) plcc52 (j) tqfq64 (u)
psd813f1v 2/110 table of contents features summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 in-system programming (isp) via jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 in-application programming (iap). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 psdsoft express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 psd architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 plds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 microcontroller bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 jtag port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 page register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power management unit (pmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 psd register description and address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 detailed operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 primary flash memory and secondary eeprom description . . . . . . . . . . . . . . . . . . . . . . . . . 18 memory operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 power-down instruction and power-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 data polling flag (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 toggle flag (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 error flag (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 erase time-out flag dq3 (flash memory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 writing to the eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 writing the otp row. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 programming flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 erasing flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 flash bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/110 psd813f1v flash erase suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 flash erase resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 flash and eeprom memory specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 flash memory and eeprom sector protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 memory select signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 memory select configuration for mcus with separate program and data spaces . . . . . . . . 31 separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 pld?s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 the turbo bit in psd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 decode pld (dpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 complex pld (cpld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 output macrocell (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 product term allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 the omc mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 the output enable of the omc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 mcu bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 psd interface to a multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 psd interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 data byte enable reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mcu bus interface examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 80c31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 80c251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 80c51xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 68hc11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 i/o ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 general port architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 mcu i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 pld i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 address out mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 address in mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
psd813f1v 4/110 data port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 peripheral i/o mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 jtag in-system programming (isp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 port configuration registers (pcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 drive select register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 data in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 data out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 output macrocells (omc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 mask macrocell register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 input macrocells (imc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 enable out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ports a and b ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 port c ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 port d ? functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 external chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 automatic power-down (apd) unit and power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 for users of the hc11 (or compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 pld power management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 sram standby mode (battery backup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 psd chip select input (csi, pd2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 reset timing and device status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 i/o pin, register and pld status at reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 programming in-circuit using the jtag serial interface . . . . . . . . . . . . . . . . . . . . . . 71 standard jtag signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 jtag extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 security, flash memory and eeprom protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 initial delivery state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ac/dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5/110 psd813f1v dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 appendix a.pqfp52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 appendix b.plcc52 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 appendix c.tqfp64 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
psd813f1v 6/110 summary description the psd family of programmable microcontroller (mcu) peripherals brings in-system programma- bility (isp) to flash memory and programmable logic. the result is a simple and flexible solution for embedded designs. psd devices combine many of the peripheral functions found in mcu based applications. psd devices integrate an optimized ?microcontrol- ler macrocell? logic architecture. the macrocell was created to address the unique requirements of embedded system designs. it allows direct con- nection between the system address/data bus and the internal psd registers to simplify communica- tion between the mcu and other supporting devic- es. the psd family offers two methods to program psd flash memory while the psd is soldered to a circuit board. in-system programming (isp) via jtag an ieee 1149.1 compliant jtag interface is in- cluded on the psd enabling the entire device (flash memory, eeprom, the pld, and all con- figuration) to be rapidly programmed while sol- dered to the circuit board. this requires no mcu participation, which means the psd can be pro- grammed anytime, even while completely blank. the innovative jtag interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: first time programming. how do i get firmware into the flash the very first time? jtag is the an- swer, program the psd while blank with no mcu involvement. inventory build-up of pre-programmed devic- es. how do i maintain an accurate count of pre- programmed flash memory and pld devices based on customer demand? how many and what version? jtag is the answer, build your hardware with blank psds soldered directly to the board and then custom program just before they are shipped to customer. no more labels on chips and no more wasted inventory. expensive sockets. how do i eliminate the need for expensive and unreliable sockets? jtag is the answer. solder the psd directly to the circuit board. program first time and subsequent times with jtag. no need to handle devices and bend the fragile leads. in-application programming (iap) two independent memory arrays (flash and ee- prom) are included so the mcu can execute code from one memory while erasing and pro- gramming the other. robust product firmware up- dates in the field are possible over any communication channel (can, ethernet, uart, j1850, etc.) using this unique architecture. de- signers are relieved of these problems: simultaneous read and write to flash memo- ry. how can the mcu program the same memory from which it is executing code? it cannot. the psd allows the mcu to operate the two memories concurrently, reading code from one while erasing and programming the other during iap. complex memory mapping. i have only a 64k- byte address space to start with. how can i map these two memories efficiently? a programmable decode pld is the answer. the concurrent psd memories can be mapped anywhere in mcu ad- dress space, segment by segment with extremely high address resolution. as an option, the second- ary flash memory can be swapped out of the sys- tem memory map when iap is complete. a built-in page register breaks the 64k-byte address limit. separate program and data space. how can i write to flash or eeprom memory while it resides in ?program? space during field firmware updates, my mcu won?t allow it! the flash psd provides means to ?reclassify? flash or eeprom memory as ?data? space during iap, then back to ?program? space when complete. psdsoft express psdsoft express, a software development tool from st, guides you through the design process step-by-step making it possible to complete an embedded mcu design capable of isp/iap in just hours. select your mcu and psdsoft express takes you through the remainder of the design with point and click entry, covering psd selection, pin definitions, programmable logic inputs and out- puts, mcu memory map definition, ansi-c code generation for your mcu, and merging your mcu firmware with the psd design. when complete, two different device programmers are supported directly from psdsoft express: flashlink (jtag) and psdpro.
7/110 psd813f1v figure 2. pqfp52 connections 39 ad15 38 ad14 37 ad13 36 ad12 35 ad11 34 ad10 33 ad9 32 ad8 31 v cc 30 ad7 29 ad6 28 ad5 27 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 6 7 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntlo 14 15 16 17 18 19 20 21 22 23 24 25 26 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ai02858
psd813f1v 8/110 figure 3. plcc52 connections pb0 pb1 pb2 pb3 pb4 pb5 gnd pb6 pb7 cntl1 cntl2 reset cntl0 pa7 pa6 pa5 pa4 pa3 gnd pa2 pa1 pa0 ad0 ad1 ad2 ad3 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 v cc ad7 ad6 ad5 ad4 pd2 pd1 pd0 pc7 pc6 pc5 pc4 v cc gnd pc3 pc2 pc1 pc0 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 47 48 49 50 51 52 1 2 3 4 5 6 7 ai02857
9/110 psd813f1v figure 4. tqfp64 connections 48 cntl0 47 ad15 46 ad14 45 ad13 44 ad12 43 ad11 42 ad10 41 ad9 40 ad8 39 v cc 38 v cc 37 ad7 36 ad6 35 ad5 34 ad4 33 ad3 pd2 pd1 pd0 pc7 pc6 pc5 v cc v cc v cc gnd gnd pc3 pc2 pc1 pc0 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nc nc pb0 pb1 pb2 pb3 pb4 pb5 gnd gnd pb6 pb7 cntl1 cntl2 reset nc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc nc pa7 pa6 pa5 pa4 pa3 gnd gnd pa2 pa1 pa0 ad0 ad1 nd ad2 ai09644
psd813f1v 10/110 pin description table 1. pin description (for the plcc52 package) pin name pin type description (1) adio0-7 30-37 i/o this is the lower address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect ad0-ad7 to this port. 2. if your mcu does not have a multiplexed address/data bus, or you are using an 80c251 in page mode, connect a0-a7 to this port. 3. if you are using an 80c51xa in burst mode, connect a4/d0 through a11/d7 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. adio8-15 39-46 i/o this is the upper address/data port. connect your mcu address or address/data bus according to the following rules: 1. if your mcu has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect a8-a15 to this port. 2. if your mcu does not have a multiplexed address/data bus, connect a8-a15 to this port. 3. if you are using an 80c251 in page mode, connect ad8-ad15 to this port. 4. if you are using an 80c51xa in burst mode, connect a12/d8 through a19/d15 to this port. ale or as latches the address. the psd drives data out only if the read signal is active and one of the psd functional blocks was selected. the addresses on this port are passed to the plds. cntl0 47 i the following control signals can be connected to this port, based on your mcu: 1. wr ? active low write strobe input. 2. r_w ? active high read/active low write input. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl1 50 i the following control signals can be connected to this port, based on your mcu: 1. rd ? active low read strobe input. 2. e ? e clock input. 3. ds ? active low data strobe input. 4. psen ? connect psen to this port when it is being used as an active low read signal. for example, when the 80c251 outputs more than 16 address bits, psen is actually the read signal. this port is connected to the plds. therefore, these signals can be used in decode and other logic equations. cntl2 49 i this port can be used to input the psen (program select enable) signal from any mcu that uses this signal for code exclusively. if your mcu does not output a program select enable signal, this port can be used as a generic input. this port is connected to the plds. reset 48 i active low reset input. resets i/o ports, pld macrocells and some of the configuration registers. must be low at power-up.
11/110 psd813f1v pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 29 28 27 25 24 23 22 21 i/o these pins make up port a. these port pins are configurable and can have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellab0-7) outputs. 3. inputs to the plds. 4. latched address outputs (see table 5 ). 5. address inputs. for example, pa0-3 could be used for a0-a3 when using an 80c51xa in burst mode. 6. as the data bus inputs d0-d7 for non-multiplexed address/data bus mcus. 7. d0/a16-d3/a19 in m37702m2 mode. 8. peripheral i/o mode. note: pa0-pa3 can only output cmos signals with an option for high slew rate. however, pa4-pa7 can be configured as cmos or open drain outputs. pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 i/o these pins make up port b. these port pins are configurable and can have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellab0-7 or mcellbc0-7) outputs. 3. inputs to the plds. 4. latched address outputs (see table 5 ). note: pb0-pb3 can only output cmos signals with an option for high slew rate. however, pb4-pb7 can be configured as cmos or open drain outputs. pc0 20 i/o pc0 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc0) output. 3. input to the plds. 4. tms input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc1 19 i/o pc1 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc1) output. 3. input to the plds. 4. tck input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc2 18 i/o pc2 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc2) output. 3. input to the plds. 4. v stby ? sram stand-by voltage input for sram battery backup. this pin can be configured as a cmos or open drain output. pc3 17 i/o pc3 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc3) output. 3. input to the plds. 4. tstat output 2 for the jtag serial interface. 5. ready/busy output for in-system parallel programming. this pin can be configured as a cmos or open drain output. pc4 14 i/o pc4 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc4) output. 3. input to the plds. 4. terr output 2 for the jtag interface. 5. battery-on indicator output (v baton ). goes high when power is being drawn from an external battery. this pin can be configured as a cmos or open drain output. pin name pin type description (1)
psd813f1v 12/110 note: 1. the pin numbers in this table are for the plcc package only. see the figure 2., page 7 , for pin numbers on other package type. 2. these functions can be multiplexed with other functions. pc5 13 i/o pc5 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc5) output. 3. input to the plds. 4. tdi input 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc6 12 i/o pc6 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc6) output. 3. input to the plds. 4. tdo output 2 for the jtag interface. this pin can be configured as a cmos or open drain output. pc7 11 i/o pc7 pin of port c. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. cpld macrocell (mcellbc7) output. 3. input to the plds. 4. dbe ? active low data byte enable input from 68hc912 type mcus. this pin can be configured as a cmos or open drain output. pd0 10 i/o pd0 pin of port d. this port pin can be configured to have the following functions: 1. ale/as input latches address output from the mcu. 2. mcu i/o ? write or read from a standard output or input port. 3. input to the plds. 4. cpld output (external chip select). pd1 9 i/o pd1 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. clkin ? clock input to the cpld macrocells, the apd unit?s power-down counter, and the cpld and array. pd2 8 i/o pd2 pin of port d. this port pin can be configured to have the following functions: 1. mcu i/o ? write to or read from a standard output or input port. 2. input to the plds. 3. cpld output (external chip select). 4. psd chip select input (csi ). when low, the mcu can access the psd memory and i/ o. when high, the psd memory blocks are disabled to conserve power. v cc 15, 38 supply voltage gnd 1, 16, 26 ground pins pin name pin type description (1)
13/110 psd813f1v figure 5. block diagram prog. mcu bus intrf. adio port cntl0, cntl1, cntl2 ad0 ? ad15 clkin clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 1 mbit main flash memory 8 sectors vstdby pa0 ? pa7 pb0 ? pb7 prog. port port c prog. port port d pc0 ? pc7 pd0 ? pd2 address/data/control bus port a ,b & c 3 ext cs to port d 24 input macrocells port a ,b & c 73 73 256 kbit secondary memory (boot or data) 4 sectors eeprom - f1 16 kbit battery backup sram runtime control and i/o registers sram select perip i/o mode selects macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pc2 ) page register embedded algorithm sector selects sector selects global config. & security ai02861f
psd813f1v 14/110 psd architectural overview psd devices contain several major functional blocks. figure 5 shows the architecture of the psd device. the functions of each block are described briefly in the following sections. many of the blocks perform multiple functions and are user config- urable. memory the psd contains the following memories: a 1 mbit flash memory a secondary 256 kbit eeprom memory a 16 kbit sram each of the memory blocks is briefly discussed in the following paragraphs. a more detailed discus- sion can be found in the section entitled memory blocks, page 18 . the 1 mbit flash memory is the main memory of the psd. it is divided into 8 equally-sized sectors that are individually selectable. the 256 kbit eeprom or flash memory is divided into 4 equally-sized sectors. each sector is individ- ually selectable. the 16 kbit sram is intended for use as a scratchpad memory or as an extension to the mi- crocontroller sram. if an external battery is con- nected to the psd?s v stby pin, data will be retained in the event of a power failure. each sector of memory can be located in a differ- ent address space as defined by the user. the ac- cess times for all memory types includes the address latching and dpld decoding time. plds the device contains two pld blocks, each opti- mized for a different function, as shown in table 2 . the functional partitioning of the plds reduces power consumption, optimizes cost/performance, and eases design entry. the decode pld (dpld) is used to decode ad- dresses and generate chip selects for the psd in- ternal memory and registers. the cpld can implement user-defined logic functions. the dpld has combinatorial outputs. the cpld has 16 out- put macrocells and 3 combinatorial outputs. the psd also has 24 input macrocells that can be con- figured as inputs to the plds. the plds receive their inputs from the pld input bus and are differ- entiated by their output destinations, number of product terms, and macrocells. the plds consume minimal power by using zero- power design techniques. the speed and power consumption of the pld is controlled by the turbo bit (zpsd only) in the pmmr0 register and other bits in the pmmr2 registers. these registers are set by the microcontroller at runtime. there is a slight penalty to pld propagation time when in- voking the zpsd features. i/o ports the psd has 27 i/o pins divided among four ports (port a, b, c, and d). each i/o pin can be individ- ually configured for different functions. ports a, b, c and d can be configured as standard mcu i/o ports, pld i/o, or latched address outputs for mi- crocontrollers using multiplexed address/data busses. the jtag pins can be enabled on port c for in- system programming (isp). ports a and b can also be configured as a data port for a n on-multiplexed bus or multiplexed ad- dress/data buses for certain types of 16-bit micro- controllers. microcontroller bus interface the psd easily interfaces with most 8-bit micro- controllers that have either multiplexed or non- multiplexed address/data busses. the device is configured to respond to the microcontroller?s con- trol signals, which are also used as inputs to the plds. where there is a requirement to use a 16- bit data bus to interface to a 16-bit microcontroller, two psds must be used. for examples, please see the section entitled mcu bus interface examples, page 47 . table 2. pld i/o name inputs outputs product terms decode pld (dpld) 73 17 42 complex pld (cpld) 73 19 140
15/110 psd813f1v jtag port in-system programming can be performed through the jtag pins on port c. this serial inter- face allows complete programming of the entire psd device. a blank device can be completely programmed. the jtag signals (tms, tck, tstat , terr , tdi, tdo) can be multiplexed with other functions on port c. table 3 indicates the jtag signals pin assignments. in-system programming (isp) using the jtag signals on port c, the entire psd device can be programmed or erased without the use of the microcontroller. the main flash memo- ry can also be programmed in-system by the mi- crocontroller executing the programming algorithms out of the eeprom or sram. the ee- prom can be programmed the same way by exe- cuting out of the main flash memory. the pld logic or other psd configuration can be pro- grammed through the jtag port or a device pro- grammer. table 4 indicates which programming methods can program different functional blocks of the psd. page register the 8-bit page register expands the address range of the microcontroller by up to 256 times. the paged address can be used as part of the ad- dress space to access external memory and pe- ripherals, or internal memory and i/o. the page register can also be used to change the address mapping of blocks of flash memory into different memory spaces for in-circuit programming. power management unit (pmu) the power management unit (pmu) in the psd gives the user control of the power consumption on selected functional blocks based on system re- quirements. the pmu includes an automatic pow- er down unit (apd) that will turn off device functions due to microcontroller inactivity. the apd unit has a power down mode that helps re- duce power consumption. the psd also has some bits that are configured at run-time by the mcu to reduce power consump- tion of the cpld. the turbo bit in the pmmr0 reg- ister can be turned off and the cpld will latch its outputs and go to sleep until the next transition on its inputs. additionally, bits in the pmmr2 register can be set by the mcu to block signals from entering the cpld to reduce power consumption. please see the section entitled power management, page 64 for more details. table 3. jtag signals on port c table 4. methods of programming different functional blocks of the psd port c pins jtag signal pc0 tms pc1 tck pc3 tstat pc4 terr pc5 tdi pc6 tdo functional block jtag programming device programmer in-system parallel programming main flash memory yes yes yes eeprom memory yes yes yes pld array (dpld and cpld) yes yes no psd configuration yes yes no optional otp row no yes yes
psd813f1v 16/110 development system the psd is supported by psdsoft express a win- dows-based (95, 98, nt) software development tool. a psd design is quickly and easily produced in a point and click environment. the designer does not need to enter hardware definition lan- guage (hdl) equations (unless desired) to define psd pin functions and memory map information. the general design flow is shown in figure 6 be- low. psdsoft express is available from our web site (www.st.com/psm) or other distribution chan- nels. psdsoft express directly supports two low cost device programmers from st, psdpro and flashlink (jtag). both of these programmers may be purchased through your local distributor/ representative, or directly from our web site using a credit card. the psd is also supported by third party device programmers, see web site for cur- rent list. figure 6. psdsoft express development tool define psd pin and node functions define general purpose logic in cpld st psd programmer *.obj file point and click definition of psd pin functions, internal nodes, and mcu system memory map psdpro, or flashlink (jtag) point and click definition of combinatorial and registered logic in cpld. access to hdl is available if needed choose mcu and psd automatically configures mcu bus interface and other psd attributes c code generation generate c code specific to psd functions user's choice of microcontroller compiler/linker *.obj file available for 3rd party programmers (conventional or jtag-isc) mcu firmware hex or s-record format ai09215 merge mcu firmware with psd configuration a composite object file is created containing mcu firmware and psd configuration.
17/110 psd813f1v psd register description and address offset table 5 shows the offset addresses to the psd registers relative to the csiop base address. the csiop space is the 256 bytes of address that is al- located by the user to the internal psd registers. table 6 provides brief descriptions of the registers in csiop space. the following section gives a more detailed description. table 5. i/o port latched address output assignments note: 1. see the section entitled i/o ports, page 52 , on how to enable the latched address output function. 2. n/a = not applicable table 6. register address offset note: 1. other registers that are not part of the i/o ports. mcu (1) port a (2) port b (2) port a (3:0) port a (7:4) port b (3:0) port b (7:4) 8051xa (8-bit) n/a address a7-a4 address a11-a8 n/a 80c251 (page mode) n/a n/a address a11-a8 address a15-a12 all other 8-bit multiplexed address a3-a0 address a7-a4 address a3-a0 address a7-a4 8-bit non-multiplexed bus n/a n/a address a3-a0 address a7-a4 register name port a port b port c port d other (1) description data in 00 01 10 11 reads port pin as input, mcu i/o input mode control 02 03 selects mode between mcu i/o or address out data out 04 05 12 13 stores data for output to port pins, mcu i/o output mode direction 06 07 14 15 configures port pin as input or output drive select 08 09 16 17 configures port pins as either cmos or open drain on some pins, while selecting high slew rate on other pins. input macrocell 0a 0b 18 reads input macrocells enable out 0c 0d 1a 1b reads the status of the output enable to the i/o port driver output macrocells ab 20 20 read ? reads output of macrocells ab write ? loads macrocell flip-flops output macrocells bc 21 21 read ? reads output of macrocells bc write ? loads macrocell flip-flops mask macrocells ab 22 22 blocks writing to the output macrocells ab mask macrocells bc 23 23 blocks writing to the output macrocells bc primary flash protection c0 read only ? flash sector protection secondary flash memory protection c2 read only ? psd security and eeprom sector protection jtag enable c7 enables jtag port pmmr0 b0 power management register 0 pmmr2 b4 power management register 2 page e0 page register vm e2 places psd memory areas in program and/or data space on an individual basis.
psd813f1v 18/110 detailed operation as shown in figure 5., page 13 , the psd consists of six major types of functional blocks: memory blocks pld blocks mcu bus interface i/o ports power management unit (pmu) jtag interface the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. memory blocks the psd has the following memory blocks (see table 7 ): ? the main flash memory ? secondary eeprom memory ?sram the memory select signals for these blocks origi- nate from the decode pld (dpld) and are user- defined in psdsoft express. primary flash memory and secondary eeprom description the 1mb primary flash memory is divided evenly into eight 16-kbyte sectors. the eeprom memo- ry is divided into four sectors of eight kbytes each. each sector of either memory can be separately protected from program and erase operations. flash memory may be erased on a sector-by-sec- tor basis and programmed byte-by-byte. flash sector erasure may be suspended while data is read from other sectors of memory and then re- sumed after reading. eeprom may be programmed byte-by-byte or sector-by-sector, and erasing is automatic and transparent. the integrity of the data can be se- cured with the help of software data protection (sdp). any write operation to the eeprom is in- hibited during the first five milliseconds following power-up. during a program or erase of flash, or during a write of the eeprom, the status can be output on the ready/busy (pc3) pin of port c3. this pin is set up using psdsoft express configuration. memory block select signals. the decode pld in the psd generates the chip selects for all the internal memory blocks (refer to the section entitled pld?s, page 34 ). each of the eight flash memory sectors have a flash select signal (fs0- fs7) which can contain up to three product terms. each of the four eeprom memory sectors have a select signal ( ees0-3 or csboot0-3) which can contain up to three product terms. having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. when using a microcontroller with separate program and data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other. ready/busy pin (pc3). pin pc3 can be used to output the ready/busy status of the psd. the out- put on the pin will be a ?0? (busy) when flash or eeprom memory blocks are being written to, or when the flash memory block is being erased. the output will be a ?1? (ready) when no write or erase operation is in progress. table 7. memory blocks device main flash eeprom sram psd813f1 128kb 32kb 2kb
19/110 psd813f1v memory operation the main flash and eeprom memory are ad- dressed through the microcontroller interface on the psd device. the microcontroller can access these memories in one of two ways: ? the microcontroller can execute a typical bus write or read operation just as it would if accessing a ram or rom device using standard bus cycles. ? the microcontroller can execute a specific instruction that consists of several write and read operations. this involves writing specific data patterns to special addresses within the flash or eeprom to invoke an embedded algorithm. these instructions are summarized in table 8., page 20 . typically, flash memory can be read by the micro- controller using read operations, just as it would read a rom device. however, flash memory can only be erased and programmed with specific in- structions. for example, the microcontroller can- not write a single byte directly to flash memory as one would write a byte to ram. to program a byte into flash memory, the microcontroller must exe- cute a program instruction sequence, then test the status of the programming event. this status test is achieved by a read operation or polling the ready/busy pin (pc3). the flash memory can also be read by using spe- cial instructions to retrieve particular flash device information (sector protect status and id). the eeprom is a bit different. data can be written to eeprom memory using write operations, like writing to a ram device, but the status of each write event must be checked by the microcon- troller. a write event can be one to 64 contigu- ous bytes. the status test is very similar to that used for flash memory (read operation or ready/busy ). optionally, the eeprom memory may be put into a software data protect (sdp) mode where it requires instructions, rather than operations, to alter its contents. sdp mode makes writing to eeprom much like writing to flash memory.
psd813f1v 20/110 table 8. instructions note: 1. additional sectors to be erased must be entered within 80 s. a sector address is any address within the sector. 2. flash and eeprom sector selects are active high. addresses a15-a12 are don?t cares in instruction bus cycles. 3. the reset instruction is required to return to the normal read mode if dq5 goes high or after reading the flash identifier or pro- tection status. 4. the mcu cannot invoke these instructions while executing code from eeprom. the mcu must be operating from some other memory when these instructions are performed. 5. the mcu cannot invoke these instructions while executing code from the same flash memory for which the instruction is intende d. the mcu must operate from some other memory when these instructions are executed. 6. writing to otp row is allowed only when sdp mode is disabled. instruction eeprom sector select (eesi) flash sector select (fsi) (2) cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 read flash identifier 3,5 01 aah@ x555h 55h@ xaaah 90h@ x555h read identifier with (a6,a1,a0 at 0,0,1) read otp row 4 10 aah@ x555h 55h@ xaaah 90h@ x555h read byte 1 read byte 2 read byte n read sector protection status 3,5 01 aah@ x555h 55h@ xaaah 90h@ x555h read identifier with (a6, a1; a0 = 0,1,0) program a flash byte 5 01 aah@ x555h 55h@ xaaah a0h@ x555h data@ address erase one flash sector 5 01 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 30h@ sector address 30h@ sector address 1 erase the whole flash 5 01 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 10h@ x555h suspend sector erase 5 01 b0h@ xxxxh resume sector erase 5 01 30h@ xxxxh eeprom power down 4 10 aah@ x555h 55h@ xaaah 30h@ x555h sdp enable/ eeprom write 4 10 aah@ x555h 55h@ xaaah a0h@ x555h write byte 1 write byte 2 write byte n sdp disable 4 10 aah@ x555h 55h@ xaaah 80h@ x555h aah@ x555h 55h@ xaaah 20h@ x555h write in otp row 4,6 10 aah@ x555h 55h@ xaaah b0h@ x555h write byte 1 write byte 2 write byte n return (from otp read or eeprom power-down) 4 10 f0h@ xxxx reset 3.5 01 aah@ x555h 55h@ xaaah f0h@ xxxx reset (short instruction) 5 01 f0h@ xxxx
21/110 psd813f1v instructions an instruction is defined as a sequence of specific operations. each received byte is sequentially de- coded by the psd and not executed as a standard write operation. the instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. some instructions are structured to include read operations after the initial write operations. the sequencing of any instruction must be fol- lowed exactly. any invalid combination of instruc- tion bytes or time-out between two consecutive bytes while addressing flash memory will reset the device logic into read mode (flash memory reads like a rom device). an invalid combination or time-out while addressing the eeprom block will cause the offending byte to be interpreted as a single operation. the psd supports these instructions (see table 8., page 20 ): flash memory: erase memory by chip or sector suspend or resume sector erase program a byte reset to read mode read flash identifier value read sector protection status eeprom: write data to otp row read data from otp row power down memory enable software data protect (sdp) disable sdp return from read otp row read mode or power down mode. these instructions are detailed in table 8., page 20 . for efficient decoding of the instruc- tions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. the coded cycles consist of writing the data aah to address x555h during the first cycle and data 55h to address xaaah during the second cycle. address lines a15-a12 are don?t cares during the instruction write cycles. how- ever, the appropriate sector select signal (fsi or eesi) must be selected. power-down instruction and power-up mode eeprom power down instruction. the ee- prom can enter power down mode with the help of the eeprom power down instruction (see ta- ble 8., page 20 ). once the eeprom power down instruction is decoded, the eeprom memory can- not be accessed unless a return instruction (also in table 8., page 20 ) is decoded. alternately, this power down mode will automatically occur when the apd circuit is triggered (see section entitled automatic power-down (apd) unit and power- down mode, page 65 ). therefore, this instruction is not required if the apd circuit is used. power-up mode. the psd internal logic is reset upon power-up to the read mode. any write op- eration to the eeprom is inhibited during the first 5ms following power-up. the fsi and eesi select signals, along with the write strobe signal, must be in the false state during power-up for maximum se- curity of the data contents and to remove the pos- sibility of a byte being written on the first edge of a write strobe signal. any write cycle initiation is locked when v cc is below v lko .
psd813f1v 22/110 read under typical conditions, the microcontroller may read the flash or eeprom memory using read operations just as it would a rom or ram device. alternately, the microcontroller may use read op- erations to obtain status information about a pro- gram or erase operation in progress. lastly, the microcontroller may use instructions to read spe- cial data from these memories. the following sec- tions describe these read functions. read memory contents. main flash is placed in the read mode after power-up, chip reset, or a reset flash instruction (see table 8., page 20 ). the microcontroller can read the memory contents of main flash or eeprom by using read opera- tions any time the read operation is not part of an instruction sequence. read main flash memory identifier. the main flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 8 ). during the read operation, ad- dress bits a6, a1, and a0 must be 0,0,1, respec- tively, and the appropriate sector select signal (fsi) must be active. the flash id is e3h for the psd. the mcu can read the id only when it is ex- ecuting from the eeprom. read main flash memory sector protection status. the main flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see table 8., page 20 ). during the read operation, address bits a6, a1, and a0 must be 0,1,0, respectively, while the chip select fsi designates the flash sector whose protection has to be verified. the read operation will pro- duce 01h if the flash sector is protected, or 00h if the sector is not protected. the sector protection status for all nvm blocks (main flash or eeprom) can be read by the mi- crocontroller accessing the flash protection and psd/ee protection registers in psd i/o space. see flash memory and eeprom sector protect, page 30 for register definitions. reading the otp row. there are 64 bytes of one-time-programmable (otp) memory that re- side in eeprom. these 64 bytes are in addition to the 32 kbytes of eeprom memory. a read of the otp row is done with an instruction composed of at least 4 operations: 3 specific write opera- tions and one to 64 read operations (see table 8., page 20 ). during the read operation(s), ad- dress bit a6 must be zero, while address bits a5- a0 define the otp row byte to be read while any eeprom sector select signal (eesi) is active. af- ter reading the last byte, an eeprom return in- struction must be executed (see table 8., page 20 ). reading the erase/program status bits. the psd provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of flash memo- ry. bits are also available to show the status of writes to eeprom. these status bits minimize the time that the microcontroller spends perform- ing these tasks and are defined in table 9 . the status bits can be read as many times as needed. for flash memory, the microcontroller can per- form a read operation to obtain these status bits while an erase or program instruction is being ex- ecuted by the embedded algorithm. see the sec- tion entitled programming flash memory, page 27 for details. for eeprom not in sdp mode, the microcontrol- ler can perform a read operation to obtain these status bits just after a data write operation. the microcontroller may write one to 64 bytes before reading the status bits. see the section entitled writing to the eeprom, page 24 for details. for eeprom in sdp mode, the microcontroller will perform a r ead operation to obtain these sta- tus bits while an sdp write instruction is being ex- ecuted by the embedded algorithm. see section entitled eeprom software data protect (sdp), page 24 for details. table 9. status bit note: 1. x = not guaranteed value, can be read either 1 or 0. 2. dq7-dq0 represent the data bus bits, d7-d0. 3. fsi and eesi are active high. device fsi/ csbooti eesi dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 flash v ih v il data polling to g g l e flag error flag x erase timeout xxx eeprom v il v ih data polling to g g l e flag xxx xxx
23/110 psd813f1v data polling flag (dq7) when erasing or programming the flash memory (or when writing into the eeprom memory), bit dq7 outputs the complement of the bit being en- tered for programming/writing on dq7. once the program instruction or the write operation is completed, the true logic value is read on dq7 (in a read operation). flash memory specific fea- tures: ? data polling is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). it must be performed at the address being programmed or at an address within the flash sector being erased. ? during an erase instruction, dq7 outputs a ?0.? after completion of the instruction, dq7 will output the last bit programmed (it is a ?1? after erasing). ? if the byte to be programmed is in a protected flash sector, the instruction is ignored. ? if all the flash sectors to be erased are protected, dq7 will be set to ?0? for about 100s, and then return to the previous addressed byte. no erasure will be performed. toggle flag (dq6) the psd offers another way for determining when the eeprom write or the flash memory program instruction is completed. during the internal write operation and when either the fsi or eesi is true, the dq6 will toggle from ?0? to ?1? and ?1? to ?0? on subsequent attempts to read any byte of the memory. when the internal cycle is complete, the toggling will stop and t he data read on the data bus d0-7 is the addressed memory byte. the device is now accessible for a new read or write operation. the operation is finished when two successive reads yield the same output data. flash memory specific features: the toggle bit is effective after the fourth write pulse (for programming) or after the sixth write pulse (for erase). if the byte to be programmed belongs to a protected flash sector, the instruction is ignored. if all the flash sectors selected for erasure are protected, dq6 will toggle to ?0? for about 100 s and then return to the previous addressed byte. error flag (dq5) during a correct program or erase, the error bit will set to ?0.? this bit is set to ?1? when there is a failure during flash byte programming, sector erase, or bulk erase. in the case of flash programming, the error bit in- dicates the attempt to program a flash bit(s) from the programmed state ('0') to the erased state ('1'), which is not a valid operation. the error bit may also indicate a timeout condition while attempting to program a byte. in case of an error in flash sector erase or byte program, the flash sector in which the error oc- curred or to which the programmed byte belongs must no longer be used. other flash sectors may still be used. the error bit resets after the reset in- struction. erase time-out flag dq3 (flash memory only) the erase timer bit reflects the time-out period al- lowed between two consecutive sector erase in- structions. the erase timer bit is set to ?0? after a sector erase instruction for a time period of 100s + 20% unless an additional sector erase instruc- tion is decoded. after this time period or when the additional sector erase instruction is decoded, dq3 is set to ?1.?
psd813f1v 24/110 writing to the eeprom data may be written a byte at a time to the ee- prom using simple write operations, much like writing to an sram. unlike sram though, the completion of each byte write must be checked be- fore the next byte is written. to speed up this pro- cess, the psd offers a page write feature to allow writing of several bytes before checking status. to prevent inadvertent writes to eeprom, the psd offers a software data protect (sdp) mode. once enabled, sdp forces the mcu to ?unlock? the eeprom before altering its contents, much like flash memory programming. writing a byte to eeprom. a write operation is initiated when an eeprom select si gnal ( eesi) is true and the write strobe signal (wr ) into the psd is true. if the psd detects no additional writes with- in 120sec, an internal storage operation is initiat- ed. internal storage to eeprom memory technology typically takes a few milliseconds to complete. the status of the write operation is obtained by the mcu reading the data polling or toggle bits (as detailed in section entitled read, page 22 ), or the ready/busy output pin (section ready/busy pin (pc3), page 18 ). keep in mind that the mcu does not need to erase a location in eeprom before writing it. erasure is performed automatically as an internal process. writing a page to eeprom. writing data to ee- prom using page mode is more efficient than writing one byte at a time. the psd eeprom has a 64 byte volatile buffer that the mcu may fill be- fore an internal eeprom storage operation is ini- tiated. page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. to invoke page mode, the mcu must write to ee- prom locations within a single page, with no more than 120s between individual byte writes. a single page means that address lines a14 to a6 must remain constant. the mcu may write to the 64 locations on a page in any order, which is de- termined by address lines a5 to a0. as soon as 120s have expired after the last page write, the internal eeprom storage process begins and the mcu checks programming status. status is checked the same way it is for byte writes, de- scribed above. note: be aware that if the upper address bits (a14 to a6) change during page write operations, loss of data may occur. ensure that all bytes for a given page have been successfully stored in the ee- prom before proceeding to the next page. cor- rect management of mcu interrupts during eeprom page write operations is essential. eeprom software data protect (sdp). the sdp feature is useful for protecting the contents of eeprom from inadvertent write cycles that may occur during uncontrolled mcu bus conditions. these may happen if the application software gets lost or when vcc is not within normal operating range. instructions from the mcu are used to enable and disable sdp mode (see table 8., page 20 ). once enabled, the mcu must write an instruction se- quence to eeprom before writing data (much like writing to flash memory). sdp mode can be used for both byte and page writes to eeprom. the device will remain in sdp mode until the mcu is- sues a valid sdp disable instruction. psd devices are shipped with sdp mode dis- abled. however, within psdsoft express, sdp mode may be enabled as part of programming the device with a device programmer (psdpro). to enable sdp mode at run time, the mcu must write three specific data bytes at three specific memory locations, as shown in figure 7., page 25 . any further writes to eeprom when sdp is set will require th is same sequence, followed by the byte(s) to write. the first sdp enable sequence can be followed directly by the byte(s) to be writ- ten. to disable sdp mode, the mcu must write specif- ic bytes to six specific locations, as shown in fig- ure 8., page 26 . the mcu must not be executing code from ee- prom when these instructions are invoked. the mcu must be operating from some other memory when enabling or disabling sdp mode. the state of sdp mode is not changed by power on/off sequences (nonvolatile). when either the sdp enable or sdp disable instructions are is- sued from the mcu, the mcu must use the toggle bit (status bit dq6) or the ready/busy output pin to check programming status. the ready/busy output is driven low from the first write of aah @ 555h until the completion of the internal storage sequence. data polling (status bit dq7) is not sup- ported when issuing the sdp enable or sdp dis- able commands. note: using the sdp sequence (enabling, dis- abling, or writing data) is initiated when specific bytes are written to addresses on specific ?pages? of eeprom memory, with no more than 120s between writes. the addresses 555h and aaah are located on different pages of eeprom. this is how the psd distinguishes these instruc- tion sequences from ordinary writes to eeprom, which are expected to be within a single eeprom page.
25/110 psd813f1v writing the otp row writing to the otp row (64 bytes) can only be done once per byte, and is enabled by an instruc- tion. this instruction is composed of three specific write operations of data bytes at three specific memory locations followed by the data to be stored in the otp row (refer to table 8., page 20 ). during the write operations, address bit a6 must be zero, while address bits a5-a0 define the otp row byte to be written while any eeprom sector select signal (eesi) is active. writing the otp row is allowed only when sdp mode is not en- abled. figure 7. eeprom sdp enable flowcharts write aah to address 555h write 55h to address aaah write a0h to address 555h sdp is set page write instruction sdp enable algorithm write aah to address 555h write 55h to address aaah write a0h to address 555h page write instruction sdp set sdp not set write is enabled write data to be written in any address write in memory write data + sdp set after twc (write cycle time) ai09219
psd813f1v 26/110 figure 8. software data protection disable flowchart write aah to address 555h write 55h to address aaah write 80h to address 555h unprotected state after twc (write cycle time) page write instruction ai09220 write aah to address 555h write 55h to address aaah write 20h to address 555h
27/110 psd813f1v programming flash memory flash memory must be erased prior to being pro- grammed. the mcu may erase flash memory all at once or by-sector, but not byte-by-byte. a byte of flash memory erases to all logic ones (ff hex), and its bits are programmed to logic zeros. al- though erasing flash memory occurs on a sector basis, programming flash memory occurs on a byte basis. the psd main flash and optional boot flash re- quire the mcu to send an instruction to program a byte or perform an erase function (see table 8., page 20 ). this differs from eeprom, which can be programmed with simple mcu bus write operations (unless eeprom sdp mode is en- abled). once the mcu issues a flash memory program or erase instruction, it must check for the status of completion. the embedded algorithms that are in- voked inside the psd support several means to provide status to the mcu. status may be checked using any of three methods: data polling, data toggle, or the ready/busy output pin. data polling polling on dq7 is a met hod of checking whether a program or erase instruction is in progress or has completed. figure 9 shows the data polling algo- rithm. when the mcu issues a programming instruction, the embedded algorithm within the psd begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq7 of this location becomes the compliment of data bit 7of the original data byte to be pro- grammed. the mcu continues to poll this location, comparing dq7 and monitoring the error bit on dq5. when the dq7 matches data bit 7 of the original data, and the error bit at dq5 remains ?0?, then the embedded algorithm is complete. if the error bit at dq5 is ?1?, the mcu should test dq7 again since dq7 may have changed simulta- neously with dq5 (see figure 9 ). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the mcu at- tempted to program a ?1? to a bit that was not erased (not erased is logic ?0?). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed to compare the byte that was written to flash with the byte that was in- tended to be written. when using the data polling method after an erase instruction, figure 9 still applies. however, dq7 will be ?0? until the erase operation is com- plete. a ?1? on dq5 will indicate a timeout failure of the erase operation, a ?0? indicates no error. the mcu can read any location within the sector being erased to get dq7 and dq5. psdsoft express will genera te ansi c code func- tions which implement these data polling algo- rithms. figure 9. data polling flowchart read dq5 & dq7 at valid address start read dq7 fail pass ai01369b dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
psd813f1v 28/110 data toggle checking the data toggle bit on dq6 is a method of determining whether a program or erase in- struction is in progress or has completed. figure 10 shows the data toggle algorithm. when the mcu issues a programming instruction, the embedded algorithm within the psd begins. the mcu then reads the location of the byte to be programmed in flash to check status. data bit dq6 of this location will toggle each time the mcu reads this location until the embedded algorithm is complete. the mcu continues to read this loca- tion, checking dq6 and monitoring the error bit on dq5. when dq6 stops toggling (two consecutive reads yield the same value), and the error bit on dq5 remains ?0?, then the embedded algorithm is complete. if the error bit on dq5 is ?1?, the mcu should test dq6 again, since dq6 may have changed simultaneously with dq5 (see figure 10 ). the error bit at dq5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the mcu at- tempted to program a ?1? to a bit that was not erased (not erased is logic ?0?). it is suggested (as with all flash memories) to read the location again after the embedded program- ming algorithm has completed to compare the byte that was written to flash with the byte that was in- tended to be written. when using the data toggle method after an erase instruction, figure 10 still applies. dq6 will toggle until the erase operation is complete. a ?1? on dq5 will indicate a tim eout failure of the erase operation, a ?0? indicates no error. the mcu can read any location within the sector being erased to get dq6 and dq5. psdsoft express will genera te ansi c code func- tions which implement these data toggling algo- rithms. figure 10. data toggle flowchart read dq5 & dq6 start read dq6 fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle
29/110 psd813f1v erasing flash memory flash bulk erase the flash bulk erase instruction uses six write op- erations followed by a read operation of the status register, as described in table 8., page 20 . if any byte of the bulk erase instruction is wrong, the bulk erase instruction aborts and the device is re- set to the read flash memory status. during a bulk erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section entitled program- ming flash memory, page 27 . the error bit (dq5) returns a ?1? if there has been an erase fail- ure (maximum number of erase cycles have been executed). it is not necessary to program the array with 00h because the psd will automatically do this before erasing to 0ffh. during execution of the bulk erase instruction, the flash memory will not accept any instructions. flash sector erase. the sector erase instruc- tion uses six write operations, as described in ta- ble 8., page 20 . additional flash sector erase confirm commands and flash sector addresses can be written subsequently to erase other flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 s. the input of a new sector erase instruction will restart the time-out period. the status of the internal timer can be monitored through the level of dq3 (erase time-out bit). if dq3 is ?0?, the sector erase instruction has been received and the timeout is counting. if dq3 is ?1?, the timeout has expired and the psd is busy eras- ing the flash sector(s). before and during erase timeout, any instruction other than erase suspend and erase resume will abort the instruction and reset the device to read mode. it is not neces- sary to program the flash sector with 00h as the psd will do this automatically before erasing (byte=ffh). during a sector erase, the memory status may be checked by reading status bits dq5, dq6, and dq7, as detailed in section entitled program- ming flash memory, page 27 . during execution of the erase instruction, the flash block logic accepts only reset and erase suspend instructions. erasure of one flash sector may be suspended, in order to read data from an- other flash sector, and then resumed. flash erase suspend when a flash sector erase operation is in progress, the erase sus pend instruction will sus- pend the operation by writing 0b0h to any address when an appropriate chip select (fsi) is true. (see table 8., page 20 ). this allows reading of data from another flash sector after the erase op- eration has been suspended. erase suspend is accepted only during the flash sector erase in- struction execution and defaults to read mode. an erase suspend instruction executed during an erase timeout will, in addition to suspending the erase, terminate the time out. the toggle bit dq6 stops toggling when the psd internal logic is suspended. the toggle bit status must be monitored at an address within the flash sector being erased. t he toggle bit will stop tog- gling between 0.1 s and 15 s after the erase suspend instruction has been executed. the psd will then automatically be set to read flash block memory array mode. if an erase suspend instruction was executed, the following rules apply: attempting to read from a flash sector that was being erased will output invalid data. reading from a flash sector that was not being erased is valid. the flash memory cannot be programmed, and will only respond to erase resume and reset instructions (read is an operation and is ok). if a reset instruction is received, data in the flash sector that was being erased will be invalid. flash erase resume if an erase suspend instruction was previously ex- ecuted, the erase operation may be resumed by this instruction. the erase resume instruction consists of writing 030h to any address while an appropriate chip select (fsi) is true. (see table 8., page 20 .)
psd813f1v 30/110 flash and eeprom memory specific features flash memory and eeprom sector protect each flash and eeprom sector can be separate- ly protected against program and erase functions. sector protection provides additional data security because it disables all program or erase opera- tions. this mode can be activated through the jtag port or a device programmer. sector protection can be selected for each sector using the psdsoft configuration program. this will automatically protect selected sectors when the device is programmed through the jtag port or a device programmer. flash and eeprom sectors can be unprotected to allow updating of their con- tents using the jtag port or a device program- mer. the microcontroller can read (but cannot change) the sector protection bits. any attempt to program or erase a protected flash or eeprom sector will be ignored by the device. the verify operation will result in a read of the protected data. this allows a guarantee of the re- tention of the protection status. the sector protection status can be read by the mcu through the flash protection and psd/ee protection registers (csiop). see table 10. reset the reset instruction resets the internal memory logic state machine in a few milliseconds. reset is an instruction of either one write operation or three write operations (refer to table 8., page 20 ). table 10. sector protection/security bit definition ? flash protection register note: 1. bit definitions: sec_prot 1 = flash is write protected. sec_prot 0 = flash is not write protected. table 11. sector protection/security bit definition ? psd/ee protection register note: 1. bit definitions: sec_prot 1 = eeprom boot sector is write protected. sec_prot 0 = eeprom boot sector is not write protected. security_bit 0 = security bit in device has not been set. 1 = security bit in device has been set. sram the sram is a 16 kbit (2k x 8) memory. the sram is enabled when rs0?the sram chip se- lect output from the dpld?is high. rs0 can con- tain up to two product terms, allowing flexible memory mapping. the sram can be backed up using an external battery. the external battery should be connected to the v stby pin (pc2). if you have an external battery connected to the psd, the contents of the sram will be retained in the event of a power loss. the contents of the sram will be retained so long as the battery voltage remains at 2v or greater. if the supply voltage falls below the battery volt- age, an internal power switchover to the battery occurs. pin pc4 can be configured as an output that indi- cates when power is being drawn from the exter- nal battery. this v baton signal will be high with the supply voltage falls below the battery voltage and the battery on pc2 is supplying power to the internal sram. the chip select signal (rs0) for the sram, v stby , and v baton are all configured using psdsoft ex- press configuration. bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 sec7_prot sec6_prot sec5_prot sec4_prot sec3_prot sec2_prot sec1_prot sec0_prot bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 security_bit not used not used not used sec3_prot sec2_prot sec1_prot sec0_prot
31/110 psd813f1v memory select signals the main flash (fsi), eeprom (eesi), and sram (rs0) memory select signals are all out- puts of the dpld. they are setup by entering equations for them in psdsoft express. the fol- lowing rules apply to the equations for the internal chip select signals: 1. flash memory and eeprom sector select signals must not be larger than the physical sector size. 2. any main flash memory sector must not be mapped in the same memory space as another flash sector. 3. an eeprom sector must not be mapped in the same memory space as another eeprom sector. 4. sram, i/o, and peripheral i/o spaces must not overlap. 5. an eeprom sector may overlap a main flash memory sector. in case of overlap, priority will be given to the eeprom. 6. sram, i/o, and peripheral i/o spaces may overlap any other memory sector. priority will be given to the sram, i/o, or peripheral i/o. example fs0 is valid when the address is in the range of 8000h to bfffh, ees0 is valid from 8000h to 9fffh, and rs0 is valid from 8000h to 87ffh. any address in the range of rs0 will always ac- cess the sram. any address in the range of ees0 greater than 87ffh (and less than 9fffh) will au- tomatically address eeprom segment 0. any ad- dress greater than 9fffh will access the flash memory segment 0. you can see that half of the flash memory segment 0 and one-fourth of ee- prom segment 0 can not be accessed in this ex- ample. also note that an equation that defined fs1 to anywhere in the range of 8000h to bfffh would not be valid. figure 11 shows the priority levels for all memory components. any component on a higher level can overlap and has priority over any component on a lower level. components on the same level must not overlap. level one has the highest priority and level 3 has the lowest. memory select configuration for mcus with separate program and data spaces the 8031 and compatible family of microcontrol- lers, which includes the 80c51, 80c151, 80c251, 80c51xa, and the c500 family, have separate ad- dress spaces for code memory (selected using psen ) and data memory (selected using rd ). any of the memories within the psd can reside in ei- ther space or both spaces. this is controlled through manipulation of the vm register that re- sides in the psd?s csiop space. the vm register is set using psdsoft express to have an initial value. it can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. for example, i may wish to have sram and flash in data space at boot, and eeprom in program space at boot, and later swap eeprom and flash. this is easily done with the vm register by using psdsoft express to configure it for boot up and having the microcontroller change it when desired. table 12 describes the vm register. figure 11. priority level of memory and i/o components table 12. vm register level 1 sram, i /o, or peripheral i /o level 2 secondary eeprom memory highest priority lowest priority level 3 flash memory ai09221 bit 7 pio_en bit 6 bit 5 bit 4 fl_data bit 3 ee_data bit 2 fl_code bit 1 ee_code bit 0 sram_code 0 = disable pio mode not used not used 0 = rd can?t access flash memory 0 = rd can?t access eeprom 0 = psen can?t access flash memory 0 = psen can?t access eeprom 0 = psen can?t access sram 1= enable pio mode not used not used 1 = rd access flash memory 1 = rd access eeprom 1 = psen access flash memory 1 = psen access eeprom 1 = psen access sram
psd813f1v 32/110 separate space modes code memory space is separated from data mem- ory space. for example, the psen signal is used to access the program code from the flash mem- ory, while the rd signal is used to access data from the eeprom, sram and i/o ports. this configuration requires the vm register to be set to 0ch. see figure 12. combined space modes the program and data memory spaces are com- bined into one space that allows the main flash memory, eeprom, and sram to be accessed by either psen or rd . for example, to configure the main flash memory in combined space mode, bits 2 and 4 of the vm register are set to ?1? (see figure 13 ). figure 12. 80c31 memory modes - separate space figure 13. 80c31 memory mode - combined space flash memory dpld eeprom memory sram rs0 ees0-ees3 fs0-fs7 cs cs cs oe oe rd psen oe ai09222 flash memory dpld eeprom memory sram rs0 ees0-ees3 fs0-fs7 rd cs cs cs rd oe oe vm reg bit 2 psen vm reg bit 0 vm reg bit 1 vm reg bit 3 vm reg bit 4 oe ai09223
33/110 psd813f1v page register the 8-bit page register increases the addressing capability of the microcontroller by a factor of up to 256. the contents of the register can also be read by the microcontroller. the outputs of the page register (pgr0-pgr7) are inputs to the dpld decoder and can be included in the flash memory, eeprom, and sram chip select equations. if memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the cpld for general logic. figure 14 shows the page register. the eight flip flops in the register are connected to the internal data bus d0-d7. the microcontroller can write to or read from the page register. the page regis- ter can be accessed at address location csiop + e0h. figure 14. page register reset d0 - d7 r/w d0 q0 q1 q2 q3 q4 q5 q6 q7 d1 d2 d3 d4 d5 d6 d7 page register pgr0 pgr1 pgr2 pgr3 flash dpld and flash cpld internal selects and logic pld pgr4 pgr5 pgr6 pgr7 ai09224
psd813f1v 34/110 pld?s the plds bring programmable logic functionality to the psd. after specifying the logic for the plds using the psdabel tool in psdsoft express, the logic is programmed into the device and available upon power-up. the psd contains two plds: the decode pld (dpld), and the complex pld (cpld). the plds are briefly discussed in the next few paragraphs, and in more detail in the sections entitled de- code pld (dpld) and complex pld (cpld) . figure 15., page 35 shows the configuration of the plds. the dpld performs address decoding for internal and external components, such as memory, regis- ters, and i/o port selects. the cpld can be used for logic functions, such as loadable counters and shift registers, state ma- chines, and encoding and decoding logic. these logic functions can be constructed using the 16 output macrocells (omcs), 24 input macrocells (imcs), and the and array. the cpld can also be used to generate external chip selects. the and array is used to form product terms. these product terms are specified using psdabel. an input bus consisting of 73 signals is connected to the plds. the signals are shown in table 13 . the turbo bit in psd the plds in the psd can minimize power con- sumption by switching off when inputs remain un- changed for an extended time of about 70ns. setting the turbo mode bit to off (bit 3 of the pmmr0 register) automatically places the plds into standby if no inputs are changing. turbo-off mode increases propagation delays while reduc- ing power consumption. see the section entitled power management, page 64 , on how to set the turbo bit. additionally, five bits are available in the pmmr2 register to block mcu control signals from entering the plds. this reduces power consumption and can be used only when these mcu control signals are not used in pld logic equations. the plds in the psd can minimize power con- sumption by switching off when inputs remain un- changed for an extended time of about 70ns. each of the two plds has unique characteristics suited for its applications. they are described in the fol- lowing sections. table 13. dpld and cpld inputs note: 1. the address inputs are a19-a4 in 80c51xa mode. input source input name number of signals mcu address bus 1 a15-a0 16 mcu control signals cntl2-cntl0 3 reset rst 1 power-down pdn 1 port a input macrocells pa7-pa0 8 port b input macrocells pb7-pb0 8 port c input macrocells pc7-pc0 8 port d inputs pd2-pd0 3 page register pgr7-pgr0 8 macrocell ab feedback mcellab.fb7- fb0 8 macrocell bc feedback mcellbc.fb7- fb0 8 eeprom program status bit ready/busy 1
35/110 psd813f1v figure 15. pld diagram pld input bus 8 input macrocell & input ports direct macrocell input to mcu data bus csiop select sram select eeprom selects decode pld page register peripheral selects jtag select cpld pt alloc. macrocell alloc. mcellab mcellbc direct macrocell access from mcu data bus 24 input macrocell (port a,b,c) 16 output macrocell i/o ports flash memory selects 3 port d inputs to port a or b to port b or c data bus 8 8 8 4 1 1 2 1 external chip selects to port d 3 73 16 73 24 output macrocell feedback ai09225
psd813f1v 36/110 decode pld (dpld) the dpld, shown in figure 16 , is used for decod- ing the address for internal and external compo- nents. the dpld can be used to generate the following decode signals: 8 sector selects for the main flash memory (three product terms each) 4 sector selects for the eeprom (three product terms each) 1 internal sram select signal (two product terms) 1 internal csiop (psd configuration register) select signal 1 jtag select signal (enables jtag on port c) 2 internal peripheral select signals (peripheral i/o mode). figure 16. dpld logic array note: 1. the address inputs are a19-a4 in 80c51xa mode. (inputs) (24) (8) (16) (1) pdn (apd output) i /o ports (port a,b,c) (8) pgr0 - pgr7 (8) mcellab.fb [7:0] (feedbacks) mcellbc.fb [7:0] (feedbacks) a [ 15:0 ] (1) (3) (3) pd [ 2:0 ] (ale,clkin,csi) cntrl [ 2:0 ] ( read/write control signals) (1) (1) reset rd_bsy rs0 csiop psel0 psel1 8 flash memory sector selects sram select i/o decoder select peripheral i/o mode select ees 0 ees 1 ees 2 ees 3 fs0 fs7 3 3 3 3 3 3 3 3 3 3 3 3 2 jtagsel ai09226 fs1 fs2 fs3 fs6 fs5 fs4 1 1 1 1 eeprom selects
37/110 psd813f1v complex pld (cpld) the cpld can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. the cpld can also be used to generate 3 external chip selects, routed to port d. although external chip selects can be produced by any output macrocell, these three external chip selects on port d do not consume any output macrocells. as shown in figure 15., page 35 , the cpld has the following blocks: 24 input macrocells (imcs) 16 output macrocells (omcs) macrocell allocator product term allocator and array capable of generating up to 137 product terms four i/o ports. each of the blocks are described in the subsec- tions that follow. the input macrocells (imc) and output macrocells (omc) are connected to the psd internal data bus and can be directly accessed by the microcontrol- ler. this enables the mcu software to load data into the output macrocells (omc) or read data from both the input and output macrocells (imc and omc). this feature allows efficient implementation of sys- tem logic and eliminates the need to connect the data bus to the and logic array as required in most standard pld macrocell architectures. figure 17. macrocell and i/o port i/o ports cpld macrocells input macrocells latched address out mux mux mux mux mux d d q q q g d qd wr wr pdr data product term allocator dir reg. select input product terms from other macrocells polarity select up to 10 product terms clock select pr di ld d/t ck cl q d/t/jk ff select pt clear pt clock global clock pt output enable ( oe ) macrocell feedback i/o port input ale/as pt input latch gate/clock mcu load pt preset mcu data in comb. /reg select macrocell to i/o port alloc. cpld output to other i/o ports pld input bus pld input bus mcu address / data bus macrocell out to mcu data load control and array cpld output i/o pin ai02874
psd813f1v 38/110 output macrocell (omc) eight of the output macrocells (omc) are con- nected to ports a and b pins and are named as mcellab0-mcellab7. the other eight macrocells are connected to ports b and c pins and are named as mcellbc0-mcellbc7. if an mcellab out- put is not assigned to a specific pin in psdabel, the macrocell allocator will assign it to either port a or b. the same is true for a mcellbc output on port b or c. table 14 shows the macrocells and port assignment. the output macrocell (omc) architecture is shown in figure 18., page 40 . as shown in the fig- ure, there are native product terms available from the and array, and borrowed product terms avail- able (if unused) from other omcs. the polarity of the product term is controlled by the xor gate. the omc can implement either sequential logic, using the flip-flop element, or combinatorial logic. the multiplexer selects between the sequential or combinatorial logic outputs. the multiplexer output can drive a port pin and has a feedback path to the and array inputs. the flip-flop in the omc can be configured as a d, t, jk, or sr type in the psdabel program. the flip-flop?s clock, preset, and clear inputs may be driven from a product term of the and array. alter- natively, the external clkin signal can be used for the clock input to the flip-flop. the flip-flop is clocked on the rising edge of the clock input. the preset and clear are active-high inputs. each clear input can use up to two product terms. table 14. output macrocell port and data bit assignments output macrocell port assignment native product terms maximum borrowed product terms data bit for loading or reading mcellab0 port a0, b0 3 6 d0 mcellab1 port a1, b1 3 6 d1 mcellab2 port a2, b2 3 6 d2 mcellab3 port a3, b3 3 6 d3 mcellab4 port a4, b4 3 6 d4 mcellab5 port a5, b5 3 6 d5 mcellab6 port a6, b6 3 6 d6 mcellab7 port a7, b7 3 6 d7 mcellbc0 port b0, c0 4 5 d0 mcellbc1 port b1, c1 4 5 d1 mcellbc2 port b2, c2 4 5 d2 mcellbc3 port b3, c3 4 5 d3 mcellbc4 port b4, c4 4 6 d4 mcellbc5 port b5, c5 4 6 d5 mcellbc6 port b6, c6 4 6 d6 mcellbc7 port b7, c7 4 6 d7
39/110 psd813f1v product term allocator the cpld has a product term allocator. the ps- dabel compiler uses the product term allocator to borrow and place product terms from one macro- cell to another. the following list summarizes how product terms are allocated: mcellab0-mcellab7 all have three native product terms and may borrow up to six more mcellbc0-mcellbc3 all have four native product terms and may borrow up to five more mcellbc4-mcellbc7 all have four native product terms and may borrow up to six more. each macrocell may only borrow product terms from certain other macrocells. product terms al- ready in use by one macrocell are not available for another macrocell. if an equation requires more product terms than are available to it, then ?external? product terms are required, which w ill consum e other output macrocells (omc). if external product terms are used, extra delay will be added for the equation that required the extra product terms. this is called product term expansion. psdsoft express will perform th is expansion as needed. loading and reading the output macrocells (omc). the omcs occupy a memory location in the mcu address space, as defined by the csiop (refer to the i/o section). the flip-flops in each of the 16 omcs can be loaded from the data bus by a microcontroller. loading the omcs with data from the mcu takes priority over internal func- tions. as such, the preset, clear, and clock inputs to the flip-flop can be overridden by the mcu. the ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. data can be loaded to the omcs on the trailing edge of the wr signal (edge loading) or during the time that the wr signal is active (level loading). the method of loading is specified in psdsoft ex- press configuration. the omc mask register there is one mask register for each of the two groups of eight omcs. the mask registers can be used to block the loading of data to individual omcs. the default value for the mask registers is 00h, which allows loading of the omcs. when a given bit in a mask register is set to a ?1?, the mcu will be blocked from writing to the associated omc. for example, suppose mcellab0-3 are be- ing used for a state machine. you would not want a mcu write to mcellab to overwrite the state ma- chine registers. therefore, you would want to load the mask register for mcellab (mask macrocell ab) with the value 0fh. the output enable of the omc the omc can be connected to an i/o port pin as a pld output. the output enable of each port pin driver is controlled by a single product term from the and array, ored with the direction register output. the pin is enabled upon power up if no out- put enable equation is defined and if the pin is de- clared as a pld output in psdsoft express. if the omc output is declared as an internal node and not as a port pin output in the psdabel file, then the port pin can be used for other i/o func- tions. the internal node feedback can be routed as an input to the and array.
psd813f1v 40/110 figure 18. cpld output macrocell pt allocator mask reg. pt clk pt pt pt clkin feedback ( .fb ) port input and array pld input bus mux mux polarity select ld in clr q pr din comb/reg select port driver input macrocell i/o pin macrocell allocator internal data bus d [ 7:0 ] direction register clear ( .re ) programmable ff ( d / t/jk /sr ) wr enable ( .oe ) preset ( .pr ) rd macrocell cs ai02875b
41/110 psd813f1v input macrocells (imc) the cpld has 24 imcs, one for each pin on ports a, b, and c. the architecture of the imc is shown in figure 19., page 42 . the imcs are individually configurable, and can be used as a latch, register, or to pass incoming port signals prior to driving them onto the pld input bus. the outputs of the imcs can be read by the microcontroller through the internal data bus. the enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the cpld and array or the mcu address strobe (ale/as). each product term output is used to latch or clock four imcs. port in- puts 3-0 can be controlled by one product term and 7-4 by another. configurations for the imcs are specified by equa- tions written in psdabel (see application note 55). outputs of the imcs can be read by the mcu via the imc buffer. see the i/o port section on how to read the imcs. imcs can use the address strobe to latch address bits higher than a15. any latched addresses are routed to the plds as inputs. imcs are particularly useful with handshaking communication applications where two proces- sors pass data back and forth through a common mailbox. figure 20., page 43 shows a typical con- figuration where the master mcu writes to the port a data out register. this, in turn, can be read by the slave mcu via the activation of the ?slave- read? output enable product term. the slave can also write to the port a imcs and the master can then read the imcs directly. note that the ?slave-read? and ?slave-wr? signals are product terms that are derived from the slave mcu inputs rd , wr , and slave_cs.
psd813f1v 42/110 figure 19. input macrocell output macrocells bc and macrocell ab pt pt feedback and array pld input bus port driver i/o pin internal data bus d [ 7: 0 ] direction register mux mux ale/as pt q q d d g latch input macrocell enable ( .oe ) d ff input macrocell _ rd ai02876b
43/110 psd813f1v figure 20. handshaking communication using input macrocells master mcu mcu - rd mcu - rd mcu - wr slave ? wr slave ? cs mcu - wr d [ 7:0 ] d [ 7:0 ] cpld dq qd port a data out register port a input macrocell port a slave ? read slave mcu rd wr ai02877c psd
psd813f1v 44/110 mcu bus interface the ?no-glue logic? psd mcu bus interface block can be directly connected to most popular mcus and their control signals. key 8-bit mcus, with their bus types and control signals, are shown in table 15 . the interface type is specified using the psdsoft express configura- tion. table 15. mcus and their control signals note: 1. unused cntl2 pin can be configured as cpld input. other unused pins (pc7, pd0, pa3-0) can be configured for other i/o fu nc- tions. 2. ale/as input is optional for mcus with a non-multiplexed bus mcu data bus width cntl0 cntl1 cntl2 pc7 pd0 2 adio0 pa3-pa0 pa7-pa3 8031 8 wr rd psen (note 1 ) ale a0 (note 1 )(note 1 ) 80c51xa 8 wr rd psen (note 1 ) ale a4 a3-a0 (note 1 ) 80c251 8 wr psen (note 1 )(note 1 ) ale a0 (note 1 )(note 1 ) 80c251 8 wr rd psen (note 1 ) ale a0 (note 1 )(note 1 ) 80198 8 wr rd (note 1 )(note 1 ) ale a0 (note 1 )(note 1 ) 68hc11 8 r/w e (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) 68hc912 8 r/w e (note 1 ) dbe as a0 (note 1 )(note 1 ) z80 8 wr rd (note 1 )(note 1 )(note 1 ) a0 d3-d0 d7-d4 z8 8 r/w ds (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) 68330 8 r/w ds (note 1 )(note 1 ) as a0 (note 1 )(note 1 ) m37702m2 8 r/w e (note 1 )(note 1 ) ale a0 d3-d0 d7-d4
45/110 psd813f1v psd interface to a multiplexed 8-bit bus figure 21 shows an example of a system using a mcu with an 8-bit multiplexed bus and a psd. the adio port on the psd is connected directly to the mcu address/data bus. address strobe (ale/as, pd0) latches the address signals internally. latched addresses can be brought out to port a or b. the psd drives the adio data bus only when one of its internal resources is accessed and read strobe (rd , cntl1) is active. should the system address bus exceed sixteen bits, ports a, b, c, or d may be used as additional address inputs. figure 21. an example of a typical 8-bit multiplexed bus interface mcu wr rd bhe ale reset ad [ 7:0 ] a [ 15:8 ] a [ 15: 8 ] a [ 7: 0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d ( optional ) ( optional ) psd ai02878c
psd813f1v 46/110 psd interface to a non-multiplexed 8-bit bus figure 22 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a psd. the address bus is connected to the adio port, and the data bus is connected to port a. port a is in tri-state mode when the psd is not accessed by the microcontroller. should the sys- tem address bus exceed sixteen bits, ports b, c, or d may be used for additional address inputs. figure 22. an example of a typical 8-bit non-multiplexed bus interface mcu wr rd bhe ale reset d [ 7:0 ] a [ 15:0 ] a [ 23:16 ] d [ 7:0 ] adio port port a port b port c wr ( cntrl0 ) rd ( cntrl1 ) bhe ( cntrl2 ) rst ale ( pd0 ) port d (optional) psd ai02879c
47/110 psd813f1v data byte enable reference microcontrollers have different data byte orienta- tions. the following table shows how the psd in- terprets byte/word operations in different bus write configurations. even-byte refers to loca- tions with address a0 equal to zero and odd byte as locations with a0 equal to one. table 16. eight-bit data bus mcu bus interface examples figure 23 to 26 show examples of the basic con- nections between the psd and some popular mcus. the psd control input pins are labeled as to the mcu function for which they are configured. the mcu bus interface is specified using the ps- dsoft express configuration. the first configuration is 80c31-compatible, and the bus interface to the psd is identical to that shown in figure 23 . the second and third configu- rations have the same bus connection as shown in table 17., page 48 . there is only one read input (psen ) connected to the cntl1 pin on the psd. the a16 connection to the pa0 pin allows for a larger address input to the psd. configuration 4 is shown in figure 24., page 49 . the rd signal is connected to cntl1 and the psen signal is con- nected to the cntl2. 80c31 figure 23 shows the bus interface for the 80c31, which has an 8-bit multiplexed address/data bus. the lower address byte is multiplexed with the data bus. the mcu control signals program se- lect enable (psen , cntl2), read strobe (rd , cntl1), and write strobe (wr , cntl0) may be used for accessing the internal memory and i/o ports. the ale input (pin pd0) latches the ad- dress. figure 23. interfacing the psd with an 80c31 bhe a0 d7-d0 x 0 even byte x 1 odd byte ea/vp x1 x2 reset reset int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc2 pc1 pc3 pc4 pc5 pc6 pc7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 (wr) cntl1(rd) cntl2 (psen) pd0-ale pd1 pd2 reset rd wr psen ale/p txd rxd reset 29 28 27 25 24 23 22 21 30 39 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 38 37 36 35 34 33 32 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 50 49 10 9 8 7 6 5 4 3 2 52 51 psd 80c31 ad7-ad0 ad [ 7:0 ] 21 22 23 24 25 26 27 28 17 16 29 30 a8 a9 a10 a11 a12 a13 a14 a15 rd wr psen ale 11 10 reset 20 19 18 17 14 13 12 11 ai02880c
psd813f1v 48/110 80c251 the intel 80c251 mcu features a user-config- urable bus interface with four possible bus config- urations, as shown in table 18., page 49 . the 80c251 has two major operating modes: page mode and non-page mode. in non-page mode, the data is multiplexed with the lower ad- dress byte, and ale is ac tive in every bus cycle. in page mode, data d[7:0] is multiplexed with ad- dress a[15:8]. in a bus cycle where there is a page hit, the ale signal is not active and only addresses a[7:0] are changing. the psd supports both modes. in page mode, the psd bus timing is iden- tical to non-page mode except the address hold time and setup time with respect to ale is not re- quired. the psd access time is measured from address a[7:0] valid to data in valid. table 17. interfacing the psd with the 80c251, with one read input note: 1. the a16 and a17 connections are optional. 2. in non-page-mode, ad7-ad0 connects to adio7-adio0. adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr a16 rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea a16 1 p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 ai02881c a17 1
49/110 psd813f1v figure 24. interfacing the psd with the 80c251, with rd and psen inputs table 18. 80c251 configurations configuration 80c251 read/write pins connecting to psd pins page mode 1 wr rd psen cntl0 cntl1 cntl2 non-page mode, 80c31 compatible a7-a0 multiplex with d7-d0 2 wr psen only cntl0 cntl1 non-page mode a7-a0 multiplex with d7-d0 3 wr psen only cntl0 cntl1 page mode a15-a8 multiplex with d7-d0 4 wr rd psen cntl0 cntl1 cntl2 page mode a15-a8 multiplex with d7-d0 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2(psen) pd0- ale pd1 pd2 reset 32 26 43 42 41 40 39 38 37 36 24 25 27 28 29 30 31 33 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad14 ad15 ad13 ad11 ad12 a0 a1 a2 a3 a4 a5 a6 a7 ad8 ad9 ad10 ad11 ad15 ale wr psen rd ad14 ad12 ad13 14 9 2 3 4 5 6 7 8 21 20 11 13 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p3.0/rxd p3.1/txd p3.2/int0 x2 x1 p3.3/int1 rst ea p0.1 p0.0 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 ale psen wr rd/a16 pc0 pc1 pc3 pc4 pc5 pc6 pc7 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 80c251sb psd reset reset 35 p3.4/t0 p3.5/t1 16 15 17 10 reset pc2 ai02882c
psd813f1v 50/110 80c51xa the philips 80c51xa microcontroller family sup- ports an 8- or 16-bit multiplexed bus that can have burst cycles. address bits (a3-a0) are not multi- plexed, while (a19-a4) are multiplexed with data bits (d15-d0) in 16-bit mode. in 8-bit mode, (a11- a4) are multiplexed with data bits (d7-d0). the 80c51xa can be configured to operate in eight-bit data mode. (shown in figure 25 ). the 80c51xa improves bus throughput and per- formance by executing burst cycles for code fetch- es. in burst mode, address a19-a4 are latched internally by the psd, while the 80c51xa changes the a3-a0 lines to fetch up to 16 bytes of code. the psd access time is then measured from address a3-a0 valid to data in valid. the psd bus timing requirement in burst mode is identical to the nor- mal bus cycle, except the address setup and hold time with respect to ale does not apply. figure 25. interfacing the psd with the 80c51x, 8-bit data bus adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 ( wr ) cntl1 ( rd ) cntl 2 (psen) pd0-ale pd1 pd2 reset 31 33 36 2 3 4 5 43 42 41 40 39 38 37 24 25 26 27 28 29 30 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a13 a14 a18 a19 a17 a15 a16 a0 a1 a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12 a16 a17 a18 a19 a15 a13 a14 txd1 t2ex t2 t0 rst ea/wait busw a1 a0/wrh a2 a3 a4d0 a5d1 a6d2 a7d3 a8d4 a9d5 a10d6 a11d7 a12d8 a13d9 a14d10 a15d11 a16d12 a17d13 a18d14 a19d15 psen rd wrl pc0 pc1 pc3 pc4 pc5 pc6 pc7 ale psen rd wr ale 32 19 18 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 7 9 8 16 xtal1 xtal2 rxd0 txd0 rxd1 21 20 11 13 6 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 7 6 5 4 3 2 52 51 a0 a1 a2 a3 80c51xa psd reset reset 35 17 int0 int1 14 10 15 pc2 ai02883c
51/110 psd813f1v 68hc11 figure 26 shows an interface to a 68hc11 where the psd is configured in 8-bit multiplexed mode with e and r/w settings. the dpld can generate the read and wr signals for external devices. figure 26. interfacing the psd with a 68hc11 9 10 11 12 13 14 15 16 adio0 adio1 adio2 adio3 ad104 ad105 adio6 adio7 adio8 adio9 adio10 adio11 ad1012 ad1013 adio14 adio15 cntl0 (r _ w) cntl1(e) cntl 2 pd0 ? as pd1 pd2 reset 20 21 22 23 24 25 3 5 4 6 42 41 40 39 38 37 36 35 ad0 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a14 a15 a13 a11 a12 ad1 ad2 ad3 ad4 ad5 ad6 ad7 e as r/w xt ex reset irq xirq pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc0 pc1 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w 31 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 48 8 9 10 49 50 47 8 7 17 19 18 34 33 32 43 44 45 46 47 48 49 50 52 51 30 29 28 27 29 28 27 25 24 23 22 21 20 19 18 17 14 13 12 11 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 7 6 5 4 3 2 52 51 modb 2 68hc11 psd reset reset ad7-ad0 ad7-ad0 pc2 ai02884c
psd813f1v 52/110 i/o ports there are four programmable i/o ports: ports a, b, c, and d. each of the ports is eight bits except port d, which is 3 bits. each port pin is individually user configurable, thus allowing multiple functions per port. the ports are configured using psdsoft ex- press configuration or by the mcu writing to on- chip registers in the csiop address space. the topics discussed in this section are: general port architecture port operating modes port configuration registers (pcr) port data registers individual port functionality. general port architecture the general architecture of the i/o port is shown in figure 27., page 53 . individual port architec- tures are shown in figure 29., page 60 to figure 32., page 63 . in general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. exceptions will be noted. as shown in figure 27., page 53 , the ports contain an output multiplexer whose selects are driven by the configuration bits in the control registers (ports a and b only) and psdsoft express config- uration. inputs to the multiplexer include the fol- lowing: output data from the data out register latched address outputs cpld macrocell output external chip select from cpld. the port data buffer (pdb) is a tri-state buffer that allows only one source at a time to be read. the pdb is connected to the internal data bus for feedback and can be read by the microcontroller. the data out and macrocell outputs, direction and control registers, and port pin input are all connected to the pdb. the port pin?s tri-state output driver enable is con- trolled by a two input or gate whose inputs come from the cpld and array enable product term and the direction register. if the enable product term of any of the array outputs are not defined and that port pin is not defined as a cpld output in the psdabel file, then the direction register has sole control of the buffer that drives the port pin. the contents of these registers can be altered by the microcontroller. the pdb feedback path al- lows the microcontroller to check the contents of the registers. ports a, b, and c have embedded input macro- cells (imcs). the imcs can be configured as latch- es, registers, or direct inputs to the plds. the latches and registers are clocked by the address strobe (as/ale) or a product term from the pld and array. the outputs from the imcs drive the pld input bus and can be read by the microcon- troller. see the section entitled input macrocell, page 42 . port operating modes the i/o ports have several modes of operation. some modes can be defined using psdabel, some by the microcontroller writing to the control registers in csiop space, and some by both. the modes that can only be defined using psdsoft ex- press must be programmed into the device and cannot be changed unless the device is repro- grammed. the modes that can be changed by the microcontroller can be done so dynamically at run- time. the pld i/o, data port, address input, and peripheral i/o modes are the only modes that must be defined before programming the device. all other modes can be changed by the microcon- troller at run-time. table 19., page 54 summarizes which modes are available on each port. table 22., page 57 shows how and where the different modes are config- ured. each of the port operating modes are de- scribed in the following subsections.
53/110 psd813f1v figure 27. general i/o port architecture internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ext cs ale read mux p d b cpld - input control reg. dir reg. input macrocell enable out data in output select output mux port pin data out address ai02885
psd813f1v 54/110 mcu i/o mode in the mcu i/o mode, the microcontroller uses the psd ports to expand its own i/o ports. by setting up the csiop space, the ports on the psd are mapped into the microcontroller address space. the addresses of the ports are listed in table 6., page 17 . a port pin can be put into mcu i/o mode by writing a ?0? to the corresponding bit in the control regis- ter. the mcu i/o direction may be changed by writing to the corresponding bit in the direction register, or by the output enable product term. see the section entitled peripheral i/o mode, page 56 . when the pin is configured as an output, the content of the data out register drives the pin. when configured as an input, the micro- controller can read the port input through the data in buffer. see figure 27., page 53 . ports c and d do not have control registers, and are in mcu i/o mode by default. they can be used for pld i/o if equation are written for them in ps- dabel. pld i/o mode the pld i/o mode uses a port as an input to the cpld?s input macrocells, and/or as an output from the cpld?s output macrocells. the output can be tri-stated with a control signal. this output enable control signal can be defined by a product term from the pld, or by setting the corresponding bit in the direction register to ?0.? the corresponding bit in the direction register must not be set to ?1? if the pin is defined as a pld input pin in psdabel. the pld i/o mode is specified in psdabel by de- claring the port pins, and then writing an equation assigning the pld i/o to a port. address out mode for microcontrollers with a multiplexed address/ data bus, address out mode can be used to drive latched addresses onto the port pins. these port pins can, in turn, drive external devices. either the output enable or the corresponding bits of both the direction register and control register must be set to a ?1? for pins to use address out mode. this must be done by the mcu at run-time. see table 21., page 55 for the address output pin assign- ments on ports a and b for various mcus. for non-multiplexed 8-bit bus mode, address lines a7-a0 are available to port b in address out mode. note: do not drive address lines with address out mode to an external memory device if it is intended for the mcu to boot from the external device. the mcu must first boot from psd memory so the di- rection and control register bits can be set. table 19. port operating modes note: 1. can be multiplexed with other i/o functions. port mode port a port b port c port d m cu i/ o yes ye s yes yes pld i/o mcellab outputs mcellbc outputs additional ext. cs outputs pld inputs yes no no yes ye s ye s no ye s no yes no yes no no yes yes address out yes (a7-a0 yes (a7-a0) or (a15-a8) no no a ddres s in yes ye s yes yes data port yes (d7-d0) no no no peripheral i/o yes no no no jtag isp no no yes 1 no
55/110 psd813f1v table 20. port operating mode settings note: 1. n/a = not applicable 2. the direction of the port a,b,c, and d pins are controlled by the direction register ored with the individual output enable p roduct term (.oe) from the cpld and array. 3. any of these three methods enables the jtag pins on port c. table 21. i/o port latched address output assignments note: 1. n/a = not applicable. mode defined in psdabel defined in psd configuration control register setting direction register setting vm register setting jtag enable mcu i/o declare pins only n/a 1 0 1 = output, 0 = input (note 2 ) n/a n/a pld i/o logic equations n/a n/a (note 2 ) n/a n/a data port (port a) n/a specify bus type n/a n/a n/a n/a address out (port a,b) declare pins only n/a 1 1 (note 2 ) n/a n/a address in (port a,b,c,d) logic equation for input macrocells n/a n/a n/a n/a n/a peripheral i/o (port a) logic equations (psel0 & 1) n/a n/a n/a pio bit = 1 n/a jtag isp (note 3 ) jtagsel jtag configuration n/a n/a n/a jtag_enable mcu port a (pa3-pa0) port a (pa7-pa4) port b (pb3-pb0) port b (pb7-pb4) 8051xa (8-bit) n/a 1 address a7-a4 address a11-a8 n/a 80c251 (page mode) n/a n/a address a11-a8 address a15-a12 all other 8-bit multiplexed address a3-a0 address a7-a4 address a3-a0 address a7-a4 8-bit non-multiplexed bus n/a n/a address a3-a0 address a7-a4
psd813f1v 56/110 address in mode for microcontrollers that have more than 16 ad- dress lines, the higher addresses can be connect- ed to port a, b, c, and d. the address input can be latched in the input macrocell by the address strobe (ale/as). any input that is included in the dpld equations for the pld?s flash, eeprom, or sram is considered to be an address input. data port mode port a can be used as a data bus port for a micro- controller with a non-multiplexed address/data bus. the data port is connected to the data bus of the microcontroller. the general i/o functions are disabled in port a if the port is configured as a data port. peripheral i/o mode peripheral i/o mode can be used to interface with external peripherals. in this mode, all of port a serves as a tri-stateable, bi-directional data buffer for the microcontroller. peripheral i/o mode is en- abled by setting bit 7 of the vm register to a ?1.? figure 28 shows how port a acts as a bi-direction- al buffer for the microcontroller data bus if periph- eral i/o mode is enabled. an equation for psel0 and/or psel1 must be written in psdabel. the buffer is tri-stated when psel 0 or psel1 is not active. figure 28. peripheral i/o mode rd psel0 psel1 psel vm register bit 7 wr pa0 - pa7 d0 - d7 data bus ai02886
57/110 psd813f1v jtag in-system programming (isp) port c is jtag compliant, and can be used for in- system programming (isp). you can multiplex jtag operations with other functions on port c because isp is not performed during normal sys- tem operation. for more information on the jtag port, see the section entitled programming in- circuit using the jtag serial interface, page 71 . port configuration registers (pcr) each port has a set of port configuration regis- ters (pcr) used for configuration. the contents of the registers can be accessed by the mcu through normal read/write bus cycles at the addresses given in table 6., page 17 . the addresses in ta- ble 6., page 17 are the offsets in hexadecimal from the base of the csiop register. the pins of a port are individually configurable and each bit in the register controls its respective pin. for example, bit 0 in a register refers to bit 0 of its port. the three port configuration registers (pcr), shown in table 22 , are used for setting the port configurations. the default power-up state for each register in table 22 is 00h. control register any bit reset to ?0? in the control register sets the corresponding port pin to mcu i/o mode, and a ?1? sets it to address out mode. the default mode is mcu i/o. only ports a and b have an associated control register. table 22. port configuration registers (pcr) note: 1. see table 26., page 58 for drive register bit definition. register name port mcu access control a,b write/read direction a,b,c,d write/read drive select 1 a,b,c,d write/read
psd813f1v 58/110 direction register the direction register, in conjunction with the out- put enable (except for port d), controls the direc- tion of data flow in the i/o ports. any bit set to ?1? in the direction register will cause the corre- sponding pin to be an output, and any bit set to ?0? will cause it to be an input. the default mode for all port pins is input. figure 29., page 60 and figure 30., page 61 show the port architecture diagrams for ports a/b and c, respectively. the direction of data flow for ports a, b, and c are controlled not only by the direction register, but also by the output enable product term from the pld and array. if the output enable product term is not active, the direction register has sole control of a given pin?s direction. an example of a configuration for a port with the three least significant bits set to output and the re- mainder set to input is shown in table 25 . since port d only contains three pins (shown in figure 32., page 63 ), the direction register for port d has only the three least significant bits active. drive select register the drive select register configures the pin driver as open drain or cmos for some port pins, and controls the slew rate for the other port pins. an external pull-up resistor should be used for pins configured as open drain. a pin can be configured as open drain if its corre- sponding bit in the drive select register is set to a ?1.? the default pin drive is cmos. aside: the slew rate is a measurement of the rise and fall times of an output. a higher slew rate means a faster output response and may create more electrical noise. a pin operates in a high slew rate when the corresponding bit in the drive reg- ister is set to ?1.? the default rate is slow slew. table 26 shows the drive register for ports a, b, c, and d. it summarizes which pins can be config- ured as open drain outputs and which pins the slew rate can be set for. table 23. port pin direction control, output enable p.t. not defined table 24. port pin direction control, output enable p.t. defined table 25. port direction assignment example table 26. drive register pin assignment note: 1. na = not applicable. direction register bit port pin mode 0 input 1 output direction register bit output enable p. t. port pin mode 0 0 input 0 1 output 1 0 output 1 1 output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 1 1 1 drive register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a open drain open drain open drain open drain slew rate slew rate slew rate slew rate port b open drain open drain open drain open drain slew rate slew rate slew rate slew rate port c open drain open drain open drain open drain open drain open drain open drain open drain port d na 1 na 1 na 1 na 1 na 1 slew rate slew rate slew rate
59/110 psd813f1v port data registers the port data registers, shown in table 27 , are used by the mcu to write data to or read data from the ports. table 27 shows the register name, the ports having each register type, and mcu access for each register type. the registers are described below. data in port pins are connected directly to the data in buff- er. in mcu i/o input mode, the pin input is read through the data in buffer. data out register stores output data written by the mcu in the mcu i/o output mode. the contents of the register are driven out to the pins if the direction register or the output enable product term is set to ?1.? the contents of the register can also be read back by the mcu. output macrocells (omc) the cpld output macrocells (omc) occupy a lo- cation in the microcontroller?s address space. the microcontroller can read the output of the omcs. if the mask macrocell register bits are not set, writing to the macrocell loads data to the macrocell flip flops. see the section entitled pld?s, page 34 . mask macrocell register each mask register bit corresponds to an omc flip flop. when the mask register bit is set to a ?1?, loading data into the omc flip flop is blocked. the default value is ?0? or unblocked. input macrocells (imc) the imcs can be used to latch or store external in- puts. the outputs of the imcs are routed to the pld input bus, and can be read by the microcon- troller. refer to the section entitled pld?s, page 34 for a detailed description. table 27. port data registers register name port mcu access data in a,b,c,d read ? input on pin data out a,b,c,d write/read output macrocell a,b,c read ? outputs of macrocells write ? loading macrocell flip-flop mask macrocell a,b,c write/read ? prevents loading into a given macrocell input macrocell a,b,c read ? outputs of the input macrocells enable out a,b,c read ? the output enable control of the port driver
psd813f1v 60/110 enable out the enable out register can be read by the micro- controller. it contains the output enable values for a given port. a ?1? indicates the driver is in output mode. a ?0? indicates the driver is in tri-state and the pin is in input mode. ports a and b ? functionality and structure ports a and b have similar functionality and struc- ture, as shown in figure 29 . the two ports can be configured to perform one or more of the following functions: mcu i/o mode cpld output ? macrocells mcellab7- mcellab0 can be connected to port a or port b. mcellbc7-mcellbc0 can be connected to port b or port c. cpld input ? via the input macrocells (imc). latched address output ? provide latched address output as per table 21., page 55 . address in ? additional high address inputs using the input macrocells (imc). open drain/slew rate ? pins pa3-pa0 and pb3-pb0 can be configured to fast slew rate, pins pa7-pa4 and pb7-pb4 can be configured to open drain mode. data port ? port a to d7-d0 for 8 bit non- multiplexed bus multiplexed address/data port for certain types of mcu bus interfaces. peripheral mode ? port a only figure 29. port a and port b structure internal data bus data out reg. dq d g q dq dq wr wr wr address macrocell outputs enable product term ( .oe ) ale read mux p d b cpld -input control reg. dir reg. input macrocell enable out data in output select output mux port a or b pin data out address a [ 7:0 ] or a [ 15:8 ] ai02887
61/110 psd813f1v port c ? functionality and structure port c can be configured to perform one or more of the following functions (see figure 30 ): mcu i/o mode cpld output ? mcellbc7-mcellbc0 outputs can be connected to port b or port c. cpld input ? via the input macrocells (imc) address in ? additional high address inputs using the input macrocells (imc). in-system programming (isp) ? jtag port can be enabled for programming/erase of the psd device. (see the section entitled programming in-circuit using the jtag serial interface, page 71 , for more information on jtag programming.) open drain ? port c pins can be configured in open drain mode battery backup features ? pc2 can be configured as a battery input pin (v stby ). pc4 can be configured as a battery-on indica- tor output pin (v baton ), indicating when v cc is less than v bat . port c does not support address out mode, and therefore no control register is required. pin pc7 may be configured as the dbe input in certain mcu interfaces. figure 30. port c structure note: 1. isp or battery back-up. internal data bus data out reg. dq dq wr wr mcellbc [ 7:0 ] enable product term ( .oe ) read mux p d b cpld -input dir reg. input macrocell enable out special function 1 special function 1 configuration bit data in output select output mux port c pin data out ai02888b
psd813f1v 62/110 port d ? functionality and structure port d has three i/o pins. see figure 31 and fig- ure 32., page 63 . this port does not support ad- dress out mode, and therefore no control register is required. port d can be configured to perform one or more of the following functions: mcu i/o mode cpld output ? external chip select (ecs0- ecs2) cpld input ? direct input to the cpld, no input macrocells (imc) slew rate ? pins can be set up for fast slew rate port d pins can be configured in psdsoft express as input pins for other dedicated functions: pd0 ? ale, as address strobe input pd1 ? clkin, as clock input to the macrocells flip-flops and apd counter pd2 ? csi , as active low chip select input. a high input will disabl e the flash memory, eeprom, sram and csiop. figure 31. port d structure internal data bus data out reg. dq dq wr wr ecs [ 2: 0 ] read mux p d b cpld - input dir reg. data in enable product term (.oe) output select output mux port d pin data out ai02889
63/110 psd813f1v external chip select the cpld also provides three external chip se- lect (ecs0-ecs2) outputs on port d pins that can be used to select external devices. each external chip select (ecs0-ecs2) consists of one product term that can be configured active high or low. the output enable of the pin is controlled by either the output enable product term or the direction register. (see figure 32 .) figure 32. port d external chip select signals pld input bus polarity bit pd2 pin pt2 ecs2 direction register polarity bit pd1 pin pt1 ecs1 enable (.oe) enable (.oe) direction register polarity bit pd0 pin pt0 ecs0 enable (.oe) direction register cpld and array ai02890
psd813f1v 64/110 power management the psd offers configurable power saving op- tions. these options may be used individually or in combinations, as follows: ? all memory types in a psd (flash, eeprom, and sram) are built with zero-power technology. in addition to using special silicon design methodology, zero-power technology puts the memories into standby mode when address/data inputs are not changing (zero dc current). as soon as a transition occurs on an input, the affected memory ?wakes up?, changes and latches its outputs, then goes back to standby. the designer does not have to do anything special to achieve memory standby mode when no inputs are changing? it happens automatically. the pld sections can also achieve standby mode when its inputs are not changing, as de- scribed in the section entitled pld power management, page 66 . ? like the zero-power feature, the automatic power down (apd) logic allows the psd to reduce to standby current automatically. the apd will block mcu addre ss/data signals from reaching the memories and plds. this feature is available on all psd devices. the apd unit is described in more detail in the sections entitled automatic power-down (apd) unit and power-down mode, page 65 . built in logic will monitor the address strobe of the mcu for activity. if there is no activity for a certain time period (mcu is asleep), the apd logic initiates power down mode (if enabled). once in power down mode, all address/data signals are blocked from reaching psd memories and plds, and the memories are deselected internally. this allows the memories and plds to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the mcu bus, etc.). keep in mind that any unblocked pld input signals that are changing states keeps the pld out of standby mode, but not the memories. ? the psd chip select input (csi ) on all families can be used to disable the internal memories, placing them in standby mode even if inputs are changing. this feature does not block any internal signals or disable the plds. this is a good alternative to using the apd logic, especially if your mcu has a chip select output. there is a slight penalty in memory access time when the csi signal makes its initial transition from deselected to selected. ? the pmmr registers can be written by the mcu at run-time to manage power. psd supports ?blocking bits? in these registers that are set to block designated signals from reaching both plds. current consumption of the plds is directly related to the composite frequency of the changes on their inputs (see figure 36., page 73 and figure 37., page 73 ). significant power savings can be achieved by blocking signals that are not used in dpld or cpld logic equations. the psd has a turbo bit in the pmmr0 register. this bit can be set to disable the turbo mode feature (default is turbo mode on). while turbo mode is disabled, the plds can achieve standby current when no pld inputs are changing (zero dc current). even when inputs do change, significant power can be saved at lower frequencies (ac current), compared to when turbo mode is enabled. when the turbo mode is enabled, there is a significant dc current component and the ac component is higher.
65/110 psd813f1v automatic power-down (apd) unit and power-down mode the apd unit, shown in figure 33 , puts the psd into power-down mode by monitoring the activity of address strobe (ale/as, pd0). if the apd unit is enabled, as soon as activity on address strobe (ale/as, pd0) stops, a four bit counter starts counting. if address strobe (ale/as, pd0) re- mains inactive for fifteen clock periods of clkin (pd1), the power-down (pdn) signal becomes ac- tive, and the psd enters power-down mode, as discussed next. power-down mode by default, if you enable the psd apd unit, power down mode is automatically enabled. the device will enter power down mo de if the address strobe (ale/as) remains inactive for fifteen clkin (pin pd1) clock periods. the following should be kept in mind when the psd is in power down mode: ? if the address strobe starts pulsing again, the psd will return to nor mal operation. the psd will also return to norma l operation if either the csi input returns low or the reset input returns high. ? the mcu address/data bus is blocked from all memories and plds. ? various signals can be blocked (prior to power down mode) from entering the plds by setting the appropriate bits in the pmmr registers. the blocked signals include mcu control signals and the common clock (clkin). note that blocking clkin from the plds will not block clkin from the apd unit. ? all psd memories enter standby mode and are drawing standby current. however, the plds and i/o ports do not go into standby mode because you don?t want to have to wait for the logic and i/o to ?wake-up? before their outputs can change. see table 28 for power down mode effects on psd ports. ? typical standby current are of the order of the microampere (see table 29 ). these standby current values assume that there are no transitions on any pld input. table 28. power-down mode?s effect on ports figure 33. apd unit table 29. psd timing and stand-by current during power-down mode note: 1. power-down does not affect the operation of the pld. the pld operation in this mode is based only on the turbo bit. 2. typical current consumption assuming no pld inputs are changing state and the pld turbo bit is 0. port function pin level mcu i/o no change pld out no change address out undefined data port tri-state peripheral i/o tri-state mode pld propagation delay memory access time access recovery time to normal access typical stand-by current 5v v cc 3v v cc power-down normal t pd (1) no access t lvdv 50a (2) 25a (2) apd en pmmr0 bit 1=1 ale reset csi clkin transition detection edge detect apd counter power down ( pdn ) disable bus interface eeprom select flash select sram select pd clr pd disable flash/eeprom/sram pld select ai02891
psd813f1v 66/110 for users of the hc11 (or compatible) the hc11 turns off its e clock when it sleeps. therefore, if you are using an hc11 (or compati- ble) in your design, and you wish to use the pow- er-down mode, you must not connect the e clock to clkin (pd1). you should instead connect an independent clock signal to the clkin input (pd1). the clock frequency must be less than 15 times the frequency of as. the reason for this is that if the frequency is greater than 15 times the frequency of as, the psd will keep going into power-down mode. other power saving options the psd offers other reduced power saving op- tions that are independent of the power-down mode. except for the sram stand-by and chip select input (csi , pd2) features, they are enabled by setting bits in the pmmr0 and pmmr2 regis- ters. pld power management the power and speed of the plds are controlled by the turbo bit (bit 3) in the pmmr0. by setting the bit to ?1?, the turbo mode is disabled and the plds consume zero power current when the in- puts are not switching for an extended time of 70ns. the propagation delay time will be in- creased by 10ns after the turbo bit is set to ?1? (turned off) when the inputs change at a composite frequency of less than 15 mhz. when the turbo bit is set to a ?0? (turned on), the plds run at full power and speed. the turbo bit affects the pld?s d.c. power, ac power, and propagation delay. note: blocking mcu control signals with pmmr2 bits can further reduce pld ac power consump- tion. sram standby mode (battery backup) the psd supports a battery backup operation that retains the contents of the sram in the event of a power loss. the sram has a v stby pin (pc2) that can be connected to an external battery. when v cc becomes lower than v stby then the psd will automatically connect to v stby as a power source to the sram. the sram standby current (i stby ) is typically 0.5a. the sram data retention volt- age is 2 v minimum. the battery-on indicator (v ba- ton ) can be routed to pc4. this signal indicates when the v cc has dropped below the v stby volt- age. psd chip select input (csi , pd2) pin pd2 of port d can be configured in psdsoft express as the csi input. when low, the signal se- lects and enables the internal flash, eeprom, sram, and i/o for read or write operations in- volving the psd. a high on the csi pin will disable the flash memory, eeprom, and sram, and re- duce the psd power consumption. however, the pld and i/o pins remain operational when csi is high. note: there may be a timing penalty when using the csi pin depending on the speed grade of the psd that you are using. see the timing parameter t slqv in table 63., page 95 or table 64., page 95 . input clock the psd provides the option to turn off the clkin input to the pld to save ac power consumption. the clkin is an input to the pld and array and the output macrocells. during power down mode, or, if the clkin input is not being used as part of the pld logic equation, the clock should be dis- abled to save ac power. the clkin will be dis- connected from the pld and array or the macrocells by setting bits 4 or 5 to a ?1? in pmmr0. figure 34. enable power-down flow chart enable apd set pmmr0 bit 1 = 1 psd in power down mode ale/as idle for 15 clkin clocks? reset yes no optional disable desired inputs to pld by setting pmmr0 bits 4 and 5 and pmmr2 bits 2 through 6. ai02892
67/110 psd813f1v table 30. power management mode registers pmmr0 (note 1) note: 1. the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. table 31. power management mode registers pmmr2 (note 1) note: 1. the bits of this register are cleared to zero following power-up. subsequent reset (reset ) pulses do not clear the registers. bit 0 x 0 not used, and should be set to zero. bit 1 apd enable 0 = off automatic power-down (apd) is disabled. 1 = on automatic power-down (apd) is enabled. bit 2 x 0 not used, and should be set to zero. bit 3 pld turbo 0 = on pld turbo mode is on 1 = off pld turbo mode is off, saving power. bit 4 pld array clk 0 = on clkin (pd1) input to the pld and array is connected. every change of clkin (pd1) powers-up the pld when turbo bit is 0. 1 = off clkin (pd1) input to pld and array is disconnected, saving power. bit 5 pld mcell clk 0 = on clkin (pd1) input to the pld macrocells is connected. 1 = off clkin (pd1) input to pld macrocells is disconnected, saving power. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero. bit 0 x 0 not used, and should be set to zero. bit 1 x 0 not used, and should be set to zero. bit 2 pld array cntl0 0 = on cntl0 input to the pld and array is connected. 1 = off cntl0 input to pld and array is disconnected, saving power. bit 3 pld array cntl1 0 = on cntl1 input to the pld and array is connected. 1 = off cntl1 input to pld and array is disconnected, saving power. bit 4 pld array cntl2 0 = on cntl2 input to the pld and array is connected. 1 = off cntl2 input to pld and array is disconnected, saving power. bit 5 pld array ale 0 = on ale input to the pld and array is connected. 1 = off ale input to pld and array is disconnected, saving power. bit 6 pld array dbe 0 = on dbe input to the pld and array is connected. 1 = off dbe input to pld and array is disconnected, saving power. bit 7 x 0 not used, and should be set to zero.
psd813f1v 68/110 input control signals the psd provides the option to turn off the input control signals (cntl0, cntl1, cntl2, ale, and dbe) to the pld to save ac power consumption. these control signals are inputs to the pld and array. during power down mode, or, if any of them are not being used as part of the pld logic equation, these control signals should be disabled to save ac power. they will be disconnected from the pld and array by setting bits 2, 3, 4, 5, and 6 to a ?1? in the pmmr2. table 32. apd counter operation apd enable bit ale pd polarity ale level apd counter 0 x x not counting 1 x pulsing not counting 1 1 1 counting (generates pdn after 15 clocks) 1 0 0 counting (generates pdn after 15 clocks)
69/110 psd813f1v reset timing and device status at reset power-on reset upon power-up, the psd requires a reset (re- set ) pulse of duration t nlnh-po (see tables 67 and 68 for values) after v cc is steady. during this period, the device loads internal configurations, clears some of the registers and sets the flash memory or eeprom into operating mode. after the rising edge of reset (r eset ), the psd re- mains in the reset mode for an additional period, t opr (see tables 67 and 68 for values), before the first memory access is allowed. the psd flash or eeprom memory is reset to the read mode upon power up. the fsi and eesi select signals along with the write strobe sig- nal must be in the false state during power-up re- set for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. the psd au- tomatically prevents write strobes from reaching the eeprom memory array for about 5ms (t eeh- wl ). any flash memory write cycle initiation is prevented automatically when v cc is below v lko . warm reset once the device is up and running, the device can be reset with a much shorter pulse of t nlnh (see tables 67 and 68 for values). the same t opr time is needed before the device is operational after warm reset. figure 35 shows the timing of the power on and warm reset. i/o pin, register and pld status at reset table 33., page 70 shows the i/o pin, register and pld status during power on reset, warm reset and power-down mode. pld outputs are always valid during warm reset, and they are valid in pow- er on reset once the internal psd configuration bits are loaded. this loading of psd is completed typically long before the v cc ramps up to operat- ing level. once the pld is active, the state of the outputs are determined by the psdabel equa- tions. figure 35. reset (reset ) timing t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
psd813f1v 70/110 table 33. status during power-on reset, warm reset and power-down mode note: 1. the sr_cod and periphmode bits in the vm register are always cleared to ?0? on power-on reset or warm reset. port configuration power-on reset warm reset power-down mode mcu i/o input mode input mode unchanged pld output valid after internal psd configuration bits are loaded valid depends on inputs to pld (addresses are blocked in pd mode) address out tri-stated tri-stated not defined data port tri-stated tri-stated tri-stated peripheral i/o tri-stated tri-stated tri-stated register power-on reset warm reset power-down mode pmmr0 and pmmr2 cleared to ?0? unchanged unchanged macrocells flip-flop status cleared to ?0? by internal power-on reset depends on .re and .pr equations depends on .re and .pr equations vm register 1 initialized, based on the selection in psdsoft express configuration menu initialized, based on the selection in psdsoft express configuration menu unchanged all other registers cleared to ?0? cleared to ?0? unchanged
71/110 psd813f1v programming in-circuit using the jtag serial interface the jtag interface on the psd can be enabled on port c (see table 34., page 72 ). all memory (flash and eeprom), pld logic, and psd config- uration bits may be programmed through the jtag interface. a blank part can be mounted on a printed circuit board and programmed using jtag. the standard jtag signals (i eee 1149.1) are tms, tck, tdi, and tdo. two additional signals, tstat and terr , are optional jtag extensions used to speed up program and erase operations. note: by default, on a blank psd (as shipped from factory or after erasure), four pins on port c are enabled for the basic jtag signals tms, tck, tdi, and tdo. standard jtag signals the standard jtag signals (tms, tck, tdi, and tdo) can be enabled by any of three different con- ditions that are logically ored. when enabled, tdi, tdo, tck, and tms are inputs, waiting for a serial command from an external jtag controller device (such as flashlink or automated test equipment). when the enabling command is re- ceived from the external jtag controller, tdo be- comes an output and the jtag channel is fully functional inside the psd. the same command that enables the jtag channel may optionally en- able the two additional jtag pins, tstat and terr . the following symbolic logic equation specifies the conditions enabling the four basic jtag pins (tms, tck, tdi, and tdo) on their respective port c pins. for purposes of discussion, the logic label jtag_on will be used. when jtag_on is true, the four pins are enabled for jtag. when jtag_on is false, the four pins can be used for general psd i/o. jtag_on = psdsoft_enabled + /* an nvm configuration bit inside the psd is set by the designer in the psdsoft express configuration utility. this dedicates the pins for jtag at all times (compliant with ieee 1149.1) */ microcontroller_enabled + /* the microcontroller can set a bit at run- time by writing to the psd register, jtag enable. this register is located at address csiop + offset c7h. setting the jtag_enable bit in this register will enable the pins for jtag use. this bit is cleared by a psd reset or the microcontroller. see table 35., page 72 for bit definition. */ psd_product_term_enabled; /* a dedicated product term (pt) inside the psd can be used to enable the jtag pins. this pt has the reserved name jtagsel. once defined as a node in psdabel, the designer can write an equation for jtagsel. this method is used when the port c jtag pins are multiplexed with other i/o signals. it is recommended to logically tie the node jtagsel to the jen\ signal on the flashlink cable when multiplexing jtag signals. (an1153) the psd supports jtag in-system-configuration (isc) commands, but not boundary scan. a defi- nition of these jtag-isc commands and se- quences are defined in a supplemental document available from st. st?s psdsoft express software tool and flashlink jtag programming cable im- plement these jtag-isc commands. this docu- ment is needed only as a reference for designers who use a flashlink to program their psd.
psd813f1v 72/110 jtag extensions tstat and terr are two jtag extension signals enabled by an ?isc_enable? command received over the four standard jtag pins (tms, tck, tdi, and tdo). they are used to speed programming and erase functions by indicating status on psd pins instead of having to scan the status out seri- ally using the standard jtag channel. terr will indicate if an error has occurred when erasing a sector or programming a byte in flash memory. this signal will go low (active) when an error condition occurs, and stay low until an ?isc_clear? command is executed or a chip re- set pulse is received after an ?isc-disable? com- mand. terr does not apply to eeprom. tstat behaves the same as the ready/busy sig- nal described in the section entitled ready/busy pin (pc3), page 18 . tstat will be high when the psd device is in read mode (flash memory and eeprom contents can be read). tstat will be low when flash memory programming or erase cycles are in progress, and also when data is be- ing written to eeprom. tstat and terr can be configured as open- drain type signals during an ?isc_enable? com- mand. this facilitates a wired-or connection of tstat signals from several psd devices and a wired-or connection of terr signals from those same devices. this is useful when several psd devices are ?chained? together in a jtag environ- ment. security, flash memory and eeprom protection when the security bit is set, the device cannot be read on a device programmer or through the jtag port. when using the jtag port, only a full chip erase command is allowed. all other program/ erase/verify commands are blocked. full chip erase returns the part to a non-secured blank state. the security bit can be set in psdsoft ex- press configuration. all flash memory and eeprom sectors can indi- vidually be sector protected against erasures. the sector protect bits can be set in psdsoft express configuration. table 34. jtag port signals initial delivery state when delivered from st, the psd device has all bits in the memory and plds set to '1.' the psd configuration register bits are set to '0.' the code, configuration, and pld logic are loaded using the programming procedure. information for program- ming the device is available directly from st. please contact your local sales representative. table 35. jtag enable register note: the state of reset (reset ) does not interrupt (or prevent) jtag operations if the jtag signals are dedicated by an nvm configura- tion bit (via psdsoft express). however, reset (reset ) prevents or interrupts jtag operations if the jtag enable register is used to enable the jtag signals. port c pin jtag signals description pc0 tms mode select pc1 tck clock pc3 tstat status pc4 terr error flag pc5 tdi serial data in pc6 tdo serial data out bit 0 jtag_enable 0 = off jtag port is disabled. 1 = on jtag port is enabled. bit 1 x 0 not used, and should be set to zero. bit 2 x 0 not used, and should be set to zero. bit 3 x 0 not used, and should be set to zero. bit 4 x 0 not used, and should be set to zero. bit 5 x 0 not used, and should be set to zero. bit 6 x 0 not used, and should be set to zero. bit 7 x 0 not used, and should be set to zero.
73/110 psd813f1v ac/dc parameters the following tables describe the ad and dc pa- rameters of the psd: dc electrical specification ac timing specification pld timing ? combinatorial timing ? synchronous clock mode ? asynchronous clock mode ? input macrocell timing mcu timing ? read timing ?write timing ? peripheral mode timing ? power-down and reset timing the following are issues concerning the parame- ters presented: in the dc specification the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd is in each mode. also, the supply power is considerably different if the turbo bit is ?0.? the ac power component gives the pld, eeprom and sram ma/mhz specification. figures 36 and 37 show the pld ma/mhz as a function of the number of product terms (pt) used. in the pld timing parameters, add the required delay when turbo bit is ?0.' figure 36. pld i cc /frequency consumption (5v range) figure 37. pld i cc /frequency consumption (3v range) 0 10 20 30 40 60 70 80 90 100 110 v cc = 5v 50 01015 5 20 25 highest composite frequency at pld inputs (mhz) i cc ? (ma) t u r b o o n (100% ) turbo on (25%) t u r b o o f f turbo off pt 100% pt 25% ai02894 0 10 20 30 40 50 60 v cc = 3v 01015 5 20 25 i cc ? (ma) turbo on (100%) t u r b o o n (2 5 % ) tu r b o o f f t u r b o o f f highest composite frequency at pld inputs (mhz) pt 100% pt 25% ai03100
psd813f1v 74/110 table 36. example of psd typical power calculation at v cc = 5.0v (turbo mode on) conditions highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 4mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = on calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5ma/mhz x freq ale + %sram x 1.5ma/mhz x freq ale + % pld x 2ma/mhz x freq pld + #pt x 400a/pt) = 50a x 0.90 + 0.1 x (0.8 x 2.5ma/mhz x 4mhz + 0.15 x 1.5ma/mhz x 4mhz + 2ma/mhz x 8mhz + 45 x 0.4ma/pt) = 45a + 0.1 x (8 + 0.9 + 16 + 18ma) = 45a + 0.1 x 42.9 = 45a + 4.29ma = 4.34ma this is the operating power with no eeprom write or flash memory erase cycles. calculation is based on i out = 0ma.
75/110 psd813f1v table 37. example of psd typical power calculation at v cc = 5.0v (turbo mode off) conditions highest composite pld input frequency (freq pld) = 8mhz mcu ale frequency (freq ale) = 4mhz % flash memory access = 80% % sram access = 15% % i/o access = 5% (no additional power above base) operational modes % normal = 10% % power-down mode = 90% number of product terms used (from fitter report) = 45 pt % of total product terms = 45/182 = 24.7% turbo mode = off calculation (using typical values) i cc total = ipwrdown x %pwrdown + %normal x (i cc (ac) + i cc (dc)) = ipwrdown x %pwrdown + % normal x (%flash x 2.5ma/mhz x freq ale + %sram x 1.5ma/mhz x freq ale + % pld x (from graph using freq pld)) = 50a x 0.90 + 0.1 x (0.8 x 2.5ma/mhz x 4mhz + 0.15 x 1.5ma/mhz x 4mhz + 24ma) = 45a + 0.1 x (8 + 0.9 + 24) = 45a + 0.1 x 32.9 = 45a + 3.29ma = 3.34ma this is the operating power with no eeprom write or flash memory erase cycles. calculation is based on i out = 0ma.
psd813f1v 76/110 maximum rating stressing the device above the rating listed in the absolute maximum ratings? table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 38. absolute maximum ratings note: 1. ipc/jedec j-std-020a 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 ? , r2=500 ? ) symbol parameter min. max. unit t stg storage temperature ?65 125 c t lead lead temperature during soldering (20 seconds max.) 1 235 c v io input and output voltage (q = v oh or hi-z) ?0.6 7.0 v v cc supply voltage ?0.6 7.0 v v pp device programmer supply voltage ?0.6 14.0 v v esd electrostatic discharge voltage (human body model) 2 ?2000 2000 v
77/110 psd813f1v dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristic tables that follow are de- rived from tests performed under the measure- ment conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. table 39. operating conditions (5v devices) table 40. operating conditions (3v devices) table 41. ac signal letters for pld timings note: example: t avlx = time from address valid to ale invalid. table 42. ac signal behavior symbols for pld timings note: example: t avlx = time from address valid to ale invalid. symbol parameter min. max. unit v cc supply voltage 4.5 5.5 v t a ambient operating temperature (industrial) ?40 85 c ambient operating temperature (commercial) 0 70 c symbol parameter min. max. unit v cc supply voltage 3.0 3.6 v t a ambient operating temperature (industrial) ?40 85 c ambient operating temperature (commercial) 0 70 c a address input c ceout output d input data e e input g internal wdog_on signal i interrupt input l ale input n reset input or output p port signal output qoutput data rwr , uds , lds , ds , iord, psen inputs s chip select input tr/w input w internal pdn signal b v stby output m output macrocell ttime l logic level low or ale h logic level high v valid x no longer a valid logic level zfloat pw pulse width
psd813f1v 78/110 table 43. ac measurement conditions note: 1. output hi-z is defined as the point where data out is no longer driven. table 44. capacitance note: 1. sampled only, not 100% tested. 2. typical values are for t a = 25c and nominal supply voltages. figure 38. ac measurement i/o waveform figure 39. ac measurement load circuit figure 40. switching waveforms ? key symbol parameter min. max. unit c l load capacitance 30 pf symbol parameter test condition typ. 2 max. unit c in input capacitance (for input pins) v in = 0v 46 pf c out output capacitance (for input/ output pins) v out = 0v 812 pf c vpp capacitance (for cntl2/v pp )v pp = 0v 18 25 pf 3.0v 0v test point 1.5v ai03103b device under test 2.01 v 195 ? c l = 30 pf (including scope and jig capacitance) ai03104b waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state ai03102
79/110 psd813f1v table 45. dc characteristics (5v devices) note: 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal power-down mode is active. 3. pld is in non-turbo mode, and none of the inputs are switching. 4. please see figure 36., page 73 for the pld current calculation. 5. i out = 0ma symbol parameter test condition (in addition to those in table 39 ) min. typ. max. unit v ih input high voltage 4.5v < v cc < 5.5v 2 v cc +0.5 v v il input low voltage 4.5v < v cc < 5.5v ?0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) ?0.5 0.2v cc ?0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 2.5 4.2 v v ol output low voltage i ol = 20a, v cc = 4.5v 0.01 0.1 v i ol = 8ma, v cc = 4.5v 0.25 0.45 v v oh output high voltage except v stby on i oh = ?20a, v cc = 4.5v 4.4 4.49 v i oh = ?2ma, v cc = 4.5v 2.4 3.9 v v oh1 output high voltage v stby on i oh1 = 1a v stby ? 0.8 v v stby sram stand-by voltage 2.0 v cc v i stby sram stand-by current v cc = 0v 0.5 1 a i idle idle current (v stby input) v cc > v stby ?0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power-down mode csi >v cc ?0.3v (notes 2,3 ) 50 200 a i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 < v out < v cc ?10 5 10 a i cc (dc) (note 5 ) operating supply current zpld only zpld_turbo = off, f = 0mhz (note 5 ) 0ma zpld_turbo = on, f = 0mhz 400 700 a/pt flash memory or eeprom during flash memory or eeprom write/erase only 15 30 ma read only, f = 0mhz 0 0 ma sram f = 0mhz 0 0 ma i cc (ac) (note 5 ) zpld ac adder see figure 36 , note 4 flash memory or eeprom ac adder 2.5 3.5 ma/ mhz sram ac adder 1.5 3.0 ma/ mhz
psd813f1v 80/110 table 46. dc characteristics (3v devices) note: 1. reset (reset ) has hysteresis. v il1 is valid at or below 0.2v cc ?0.1. v ih1 is valid at or above 0.8v cc . 2. csi deselected or internal pd is active. 3. i out = 0ma symbol parameter conditions min. typ. max. unit v ih high level input voltage 3.0v < v cc < 3.6v 0.7v cc v cc +0.5 v v il low level input voltage 3.0v < v cc < 3.6v ?0.5 0.8 v v ih1 reset high level input voltage (note 1 ) 0.8v cc v cc +0.5 v v il1 reset low level input voltage (note 1 ) ?0.5 0.2v cc ?0.1 v v hys reset pin hysteresis 0.3 v v lko v cc (min) for flash erase and program 1.5 2.2 v v ol output low voltage i ol = 20a, v cc = 3.0v 0.01 0.1 v i ol = 4ma, v cc = 3.0v 0.15 0.45 v v oh output high voltage except v stby on i oh = ?20a, v cc = 3.0v 2.9 2.99 v i oh = ?1ma, v cc = 3.0v 2.7 2.8 v v oh1 output high voltage v stby on i oh1 = 1a v stby ? 0.8 v v stby sram stand-by voltage 2.0 v cc v i stby sram stand-by current v cc = 0v 0.5 1 a i idle idle current (v stby input) v cc > v stby ?0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb stand-by supply current for power-down mode csi >v cc ?0.3v (notes 2 ) 25 100 a i li input leakage current v ss < v in < v cc ?1 0.1 1 a i lo output leakage current 0.45 < v in < v cc ?10 5 10 a i cc (dc) (note 3 ) operating supply current zpld only zpld_turbo = off, f = 0mhz (note 3 ) 0 a/pt zpld_turbo = on, f = 0mhz 200 400 a/pt flash memory or eeprom during flash memory or eeprom write/erase only 10 25 ma read only, f = 0mhz 0 0 ma sram f = 0mhz 0 0 ma i cc (ac) (note 3 ) zpld ac adder see figure 37., page 73 flash memory or eeprom ac adder 1.5 2.0 ma/ mhz sram ac adder 0.8 1.5 ma/ mhz
81/110 psd813f1v figure 41. input to output disable / enable figure 42. combinatorial timing pld table 47. cpld combinatorial timing (5v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd0. decrement times by given amount. 2. zpsd versions only. symbol parameter conditions -90 -12 -15 fast pt aloc turbo off 2 slew rate 1 unit min max min max min max t pd cpld input pin/ feedback to cpld combinatorial output 25 30 32 + 2 + 10 ? 2 ns t ea cpld input to cpld output enable 26 30 32 + 10 ? 2 ns t er cpld input to cpld output disable 26 30 32 + 10 ? 2 ns t arp cpld register clear or preset delay 26 30 33 + 10 ? 2 ns t arpw cpld register clear or preset pulse width 20 24 29 + 10 ns t ard cpld array delay any macrocell 16 18 22 + 2 ns ter tea input input to output enable/disable ai02863 t pd cpld input cpld output ai09228
psd813f1v 82/110 table 48. cpld combinatorial timing (3v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd0. decrement times by given amount. 2. zpsd versions only. figure 43. synchronous clock mode timing ? pld symbol parameter conditions -15 -20 pt aloc tu rbo off 2 slew rate 1 unit min max min max t pd cpld input pin/feedback to cpld combinatorial output 48 55 + 4 + 20 ? 6 ns t ea cpld input to cpld output enable 43 50 + 20 ? 6 ns t er cpld input to cpld output disable 43 50 + 20 ? 6 ns t arp cpld register clear or preset delay 48 55 + 20 ? 6 ns t arpw cpld register clear or preset pulse width 30 35 + 20 ns t ard cpld array delay any macrocell 29 33 + 4 ns t ch t cl t co t h t s clkin input registered output ai02860
83/110 psd813f1v table 49. cpld macrocell synchronous clock mode timing (5v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd0. decrement times by given amount. 2. clkin (pd1) t clcl = t ch + t cl . symbol parameter conditions -90 -12 -15 fast pt aloc turbo off slew rate 1 unit min max min max min max f max maximum frequency external feedback 1/(t s +t co ) 30.3 0 26.3 23.8 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co ?10) 43.4 8 35.7 31.25 mhz maximum frequency pipelined data 1/(t ch +t cl ) 50.0 0 41.67 33.3 mhz t s input setup time 15 18 20 + 2 + 10 ns t h input hold time 0 0 0 ns t ch clock high time clock input 10 12 15 ns t cl clock low time clock input 10 12 15 ns t co clock to output delay clock input 18 20 22 ? 2 ns t ard cpld array delay any macrocell 16 18 22 + 2 ns t min minimum clock period 2 t ch +t cl 20 24 30 ns
psd813f1v 84/110 table 50. cpld macrocell synchronous clock mode timing (3v devices) note: 1. fast slew rate output available on pa3-pa0, pb3-pb0, and pd2-pd0. 2. clkin (pd1) t clcl = t ch + t cl . figure 44. asynchronous reset / preset figure 45. asynchronous clock mode timing (product term clock) symbol parameter conditions -15 -20 pt aloc turbo off slew rate 1 unit min max min max f max maximum frequency external feedback 1/(t s +t co ) 17.8 14.7 mhz maximum frequency internal feedback (f cnt ) 1/(t s +t co ?10) 19.6 17.2 mhz maximum frequency pipelined data 1/(t ch +t cl ) 33.3 31.2 mhz t s input setup time 27 35 + 4 + 20 ns t h input hold time 0 0 ns t ch clock high time clock input 15 16 ns t cl clock low time clock input 15 16 ns t co clock to output delay clock input 35 39 ? 6 ns t ard cpld array delay any macrocell 29 33 + 4 ns t min minimum clock period 2 t ch +t cl 29 32 ns tarp register output tarpw reset/preset input ai02864 tcha tcla tcoa tha tsa clock input registered output ai02859
85/110 psd813f1v table 51. cpld macrocell asynchronous clock mode timing (5v devices) note: 1. zpsd versions only. symbol parameter conditions -90 -12 -15 pt aloc turbo off 1 slew rate unit min max min max min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 26.3 2 23.25 20.4 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa ?10) 35.7 1 30.30 25.64 mhz maximum frequency pipelined data 1/(t cha +t cla ) 41.6 7 35.71 33.3 mhz t sa input setup time 8 10 12 + 2 + 10 ns t ha input hold time 12 14 14 ns t cha clock input high time 12 14 15 + 10 ns t cla clock input low time 12 14 15 + 10 ns t coa clock to output delay 30 33 37 + 10 ? 2 ns t arda cpld array delay any macrocell 16 18 22 + 2 ns t mina minimum clock period 1/f cnta 28 33 39 ns
psd813f1v 86/110 table 52. cpld macrocell asynchronous clock mode timing (3v devices) note: 1. zpsd versions only. symbol parameter conditions -15 -20 pt aloc turbo off 1 slew rate unit min max min max f maxa maximum frequency external feedback 1/(t sa +t coa ) 19.2 16.9 mhz maximum frequency internal feedback (f cnta ) 1/(t sa +t coa ?10) 23.8 20.4 mhz maximum frequency pipelined data 1/(t cha +t cla ) 27 24.4 mhz t sa input setup time 12 13 + 4 + 20 ns t ha input hold time 15 17 ns t cha clock high time 22 25 + 20 ns t cla clock low time 15 16 + 20 ns t coa clock to output delay 40 46 + 20 ? 6 ns t ard cpld array delay any macrocell 29 33 + 4 ns t mina minimum clock period 1/f cnta 42 49 ns
87/110 psd813f1v figure 46. input macrocell timing (product term clock) table 53. input macrocell timing (5v devices) note: 1. inputs from port a, b, and c relative to register/ latch clock from the pld. ale/as latch timings refer to t avlx and t lxax . 2. zpsd versions only. table 54. input macrocell timing (3v devices) note: 1. inputs from port a, b, and c relative to register/latch clock from the pld. ale latch timings refer to t avlx and t lxax . 2. zpsd versions only. symbol parameter conditions -90 -12 -15 pt aloc turbo off 2 unit min max min max min max t is input setup time (note 1 ) 000 ns t ih input hold time (note 1 ) 20 22 26 + 10 ns t inh nib input high time (note 1 ) 12 15 18 ns t inl nib input low time (note 1 ) 12 15 18 ns t ino nib input to combinatorial delay (note 1 ) 46 50 59 + 2 + 10 ns symbol parameter conditions -15 -20 pt aloc turbo off 2 unit min max min max t is input setup time (note 1 ) 00 ns t ih input hold time (note 1 ) 25 30 + 20 ns t inh nib input high time (note 1 ) 13 15 ns t inl nib input low time (note 1 ) 13 15 ns t ino nib input to combinatorial delay (note 1 ) 62 70 + 4 + 20 ns t inh t inl t ino t ih t is pt clock input output ai03101
psd813f1v 88/110 figure 47. read timing note: 1. t avlx and t lxax are not required for 80c251 in page mode or 80c51xa in burst mode. t avlx t lxax 1 t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out ale /as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) e r/w ai02895
89/110 psd813f1v table 55. read timing (5v devices) note: 1. rd timing has the same timing as ds , lds , uds , and psen signals. 2. rd and psen have the same timing. 3. any input used to select an internal psd function. 4. in multiplexed mode, latched addresses generated from adio delay to address output on any port. 5. rd timing has the same timing as ds , lds , and uds signals. 6. in turbo off mode, add 10ns to t avqv . symbol parameter conditions -90 -12 -15 turbo off unit minmaxminmaxminmax t lvlx ale or as pulse width 20 22 28 ns t avlx address setup time (note 3 ) 6 8 10 ns t lxax address hold time (note 3 ) 8911 ns t avqv address valid to data valid (notes 3,6 ) 90 120 150 + 10 ns t slqv cs valid to data valid 100 135 150 ns t rlqv rd to data valid 8-bit bus (note 5 ) 32 35 40 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 38 42 45 ns t rhqx rd data hold time (note 1 ) 000 ns t rlrh rd pulse width (note 1 ) 32 35 38 ns t rhqz rd to data high-z (note 1 ) 25 35 38 ns t ehel e pulse width 32 36 38 ns t theh r/w setup time to enable 10 13 18 ns t eltl r/w hold time after enable 0 0 0 ns t avpv address input valid to address output delay (note 4 ) 25 28 32 ns
psd813f1v 90/110 table 56. read timing (3v devices) note: 1. rd timing has the same timing as ds , lds , uds , and psen signals. 2. rd and psen have the same timing for 8031. 3. any input used to select an internal psd function. 4. in multiplexed mode latched address generated from adio delay to address output on any port. 5. rd timing has the same timing as ds , lds , and uds signals. 6. in turbo off mode, add 20ns to t avqv . symbol parameter conditions -15 -20 turbo off unit min max min max t lvlx ale or as pulse width 26 30 ns t avlx address setup time (note 3 ) 10 12 ns t lxax address hold time (note 3 ) 12 14 ns t avqv address valid to data valid (note 3,6 ) 150 200 + 20 ns t slqv cs valid to data valid 150 200 ns t rlqv rd to data valid 8-bit bus (note 5 ) 35 40 ns rd or psen to data valid 8-bit bus, 8031, 80251 (note 2 ) 50 55 ns t rhqx rd data hold time (note 1 ) 00 ns t rlrh rd pulse width (also ds , lds , uds )4045ns rd or psen pulse width (8031, 80251) 55 60 ns t rhqz rd to data high-z (note 1 ) 40 45 ns t ehel e pulse width 45 52 ns t theh r/w setup time to enable 18 20 ns t eltl r/w hold time after enable 0 0 ns t avpv address input valid to address output delay (note 4 ) 35 40 ns
91/110 psd813f1v figure 48. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlmv t wlwh t dv wh t theh t avpv address valid address valid data valid data valid address out t whpv standard mcu i/o out ale / as a/d multiplexed bus address non-multiplexed bus data non-multiplexed bus csi wr (ds) e r/ w ai02896
psd813f1v 92/110 table 57. write, erase and program timing (5v devices) note: 1. any input used to select an internal psd function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e, lds , uds , wrl , and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. t whax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. symbol parameter conditions -90 -12 -15 unit min max min max min max t lvlx ale or as pulse width 20 22 28 ns t avlx address setup time (note 1 ) 6 8 10 ns t lxax address hold time (note 1 ) 8911ns t avwl address valid to leading edge of wr (notes 1,3 ) 15 18 20 ns t slwl cs valid to leading edge of wr (note 3 ) 15 18 20 ns t dvwh wr data setup time (note 3 ) 35 40 45 ns t whdx wr data hold time (note 3 ) 555ns t wlwh wr pulse width (note 3 ) 35 40 45 ns t whax1 trailing edge of wr to address invalid (note 3 ) 8 9 10 ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 000ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 30 35 38 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 55 60 65 ns t avpv address input valid to address output delay (note 2 ) 25 28 30 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 55 60 65 ns
93/110 psd813f1v table 58. write timing (3v devices) note: 1. any input used to select an internal psd function. 2. in multiplexed mode, latched address generated from adio delay to address output on any port. 3. wr has the same timing as e, lds , uds , wrl , and wrh signals. 4. assuming data is stable before active write signal. 5. assuming write is active before data becomes valid. 6. twhax2 is the address hold time for dpld inputs that are used to generate sector select signals for internal psd memory. table 59. flash program, write and erase times (5v devices) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid t q7vqv time units before the data byte, dq0-dq7, is valid for reading. symbol parameter conditions -15 -20 unit minmaxminmax t lvlx ale or as pulse width 26 30 t avlx address setup time (note 1 ) 10 12 ns t lxax address hold time (note 1 ) 12 14 ns t avwl address valid to leading edge of wr (notes 1,3 ) 20 25 ns t slwl cs valid to leading edge of wr (note 3 ) 20 25 ns t dvwh wr data setup time (note 3 ) 45 50 ns t whdx wr data hold time (note 3 ) 810ns t wlwh wr pulse width (note 3 ) 48 53 ns t whax1 trailing edge of wr to address invalid (note 3 ) 12 17 ns t whax2 trailing edge of wr to dpld address invalid (note 3,6 ) 00ns t whpv trailing edge of wr to port output valid using i/o port data register (note 3 ) 45 50 ns t dvmv data valid to port output valid using macrocell register preset/clear (notes 3,5 ) 90 100 ns t avpv address input valid to address output delay (note 2 ) 48 55 ns t wlmv wr valid to port output valid using macrocell register preset/clear (notes 3,4 ) 90 100 ns symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns
psd813f1v 94/110 table 60. flash program, write and erase times (3v devices) note: 1. programmed to all zero before erase. 2. the polling status, dq7, is valid t q7vqv time units before the data byte, dq0-dq7, is valid for reading. table 61. eeprom write times (5v devi ces) note: 1. if the maximum time has elapsed between successive write cycles to an eeprom page, the transfer of this data to eeprom cells will begin. also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. these specifications are for writing a page to eeprom cells. table 62. eeprom write times (3v devi ces) note: 1. if the maximum time has elapsed between successive write cycles to an eeprom page, the transfer of this data to eeprom cells will begin. also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. these specifications are for writing a page to eeprom cells. symbol parameter min. typ. max. unit flash program 8.5 s flash bulk erase 1 (pre-programmed) 330s flash bulk erase (not pre-programmed) 10 s t whqv3 sector erase (pre-programmed) 1 30 s t whqv2 sector erase (not pre-programmed) 2.2 s t whqv1 byte program 14 1200 s program / erase cycles (per sector) 100,000 cycles t whwlo sector erase time-out 100 s t q7vqv dq7 valid to output (dq7-dq0) valid (data polling) 2 30 ns symbol parameter min typ max unit t eehwl write protect after power up 5 ms t blc eeprom byte load cycle timing (note 1 ) 0.2 120 s t wcb eeprom byte write cycle time 4 10 ms t wcp eeprom page write cycle time (note 2 ) 630ms program/erase cycles (per sector) 10,000 cycles symbol parameter min typ max unit t eehwl write protect after power up 5 ms t blc eeprom byte load cycle timing (note 1 ) 0.2 120 s t wcb eeprom byte write cycle time 4 10 ms t wcp eeprom page write cycle time (note 2 ) 630ms program/erase cycles (per sector) 10,000 cycles
95/110 psd813f1v figure 49. peripheral i/o read timing table 63. port a peripheral data mode read timing (5v devices) table 64. port a peripheral data mode read timing (3v devices) symbol parameter conditions -90 -12 -15 turbo off unit minmaxminmaxminmax t avqv?pa address valid to data valid (note 3 ) 40 45 45 + 10 ns t slqv?pa csi valid to data valid 35 40 45 + 10 ns t rlqv?pa rd to data valid (notes 1,4 ) 32 35 40 ns rd to data valid 8031 mode 38 42 45 ns t dvqv?pa data in to data out valid 30 35 38 ns t qxrh?pa rd data hold time 0 0 0 ns t rlrh?pa rd pulse width (note 1 ) 32 35 38 ns t rhqz?pa rd to data high-z (note 1 ) 25 28 30 ns symbol parameter conditions -15 -20 turb o off unit min max min max t avqv?pa address valid to data valid (note 3 ) 55 60 + 20 ns t slqv?pa csi valid to data valid 45 50 + 20 ns t rlqv?pa rd to data valid (notes 1,4 ) 40 45 ns rd to data valid 8031 mode 45 50 ns t dvqv?pa data in to data out valid 60 65 ns t qxrh?pa rd data hold time 0 0 ns t rlrh?pa rd pulse width (note 1 ) 36 46 ns t rhqz?pa rd to data high-z (note 1 ) 40 45 ns t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address data valid ale /as a /d bus rd data on port a csi ai02897
psd813f1v 96/110 figure 50. peripheral i/o write timing table 65. port a peripheral data mode write timing (5v devices) note: 1. rd has the same timing as ds , lds , uds , and psen (in 8031 combined mode). 2. wr has the same timing as the e, lds , uds , wrl , and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. table 66. port a peripheral data mode write timing (3v devices) note: 1. rd has the same timing as ds , lds , uds , and psen (in 8031 combined mode) signals. 2. wr has the same timing as the e, lds , uds , wrl , and wrh signals. 3. any input used to select port a data peripheral mode. 4. data is already stable on port a. 5. data stable on adio pins to data on port a. symbol parameter conditions -90 -12 -15 unit min max min max min max t wlqv?pa wr to data propagation delay (note 2 ) 35 38 40 ns t dvqv?pa data to port a data propagation delay (note 5 ) 30 35 38 ns t whqz?pa wr invalid to port a tri-state (note 2 ) 25 30 33 ns symbol parameter conditions -15 -20 unit min max min max t wlqv?pa wr to data propagation delay (note 2 ) 45 55 ns t dvqv?pa data to port a data propagation delay (note 5 ) 40 45 ns t whqz?pa wr invalid to port a tri-state (note 2 ) 33 35 ns tdvqv (pa) twlqv (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as ai02898
97/110 psd813f1v figure 51. reset (reset ) timing table 67. reset (r eset ) timing (5v devices) note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. warm reset aborts flash memory program or erase cycles, and puts the device in read mode. table 68. reset (r eset ) timing (3v devices) note: 1. reset (reset ) does not reset flash memory program or erase cycles. 2. t nlnh-po is 10ms for devices manufactured before the rev.a. table 69. v stbyon timing (5v devices) table 70. v stbyon timing (3v devices) symbol parameter conditions min max unit t nlnh reset active low time 1 150 ns t nlnh?po power on reset active low time 1 ms t opr reset high to operational device 120 ns symbol parameter conditions min max unit t nlnh reset active low time 1 300 ns t nlnh?po power on reset active low time 2 1ms t opr reset high to operational device 300 ns symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 20 s t bxbl v stby off detection to v stbyon output low (note 1 ) 20 s symbol parameter conditions min typ max unit t bvbh v stby detection to v stbyon output high (note 1 ) 2.0 s t bxbl v stby off detection to v stbyon output low (note 1 ) 2.0 s t nlnh-po t opr ai02866b reset t nlnh t nlnh-a t opr v cc v cc (min) power-on reset warm reset
psd813f1v 98/110 figure 52. isc timing table 71. isc timing (5v devices) note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. symbol parameter conditions -90 -12 -15 unit min max min max min max t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 18 16 14 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 26 29 31 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 26 29 31 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 222mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 240 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 240 240 ns t iscpsu isc port set up time 8 10 10 ns t iscph isc port hold up time 5 5 5 ns t iscpco isc port clock to output 23 24 25 ns t iscpzv isc port high-impedance to valid output 23 24 25 ns t iscpvz isc port valid output to high-impedance 23 24 25 ns iscch tck tdi/tms isc outputs/tdo isc outputs/tdo t isccl t iscph t iscpsu t iscpvz t iscpzv t iscpco t ai02865
99/110 psd813f1v table 72. isc timing (3v devices) note: 1. for non-pld programming, erase or in isc by-pass mode. 2. for program or erase pld only. table 73. power-down timing (5v devices) note: 1. t clcl is the period of clkin (pd1). table 74. power-down timing (3v devices) note: 1. t clcl is the period of clkin (pd1). symbol parameter conditions -15 -20 unit minmaxminmax t isccf clock (tck, pc1) frequency (except for pld) (note 1 ) 10 9 mhz t iscch clock (tck, pc1) high time (except for pld) (note 1 ) 45 51 ns t isccl clock (tck, pc1) low time (except for pld) (note 1 ) 45 51 ns t isccfp clock (tck, pc1) frequency (pld only) (note 2 ) 22mhz t iscchp clock (tck, pc1) high time (pld only) (note 2 ) 240 240 ns t iscclp clock (tck, pc1) low time (pld only) (note 2 ) 240 240 ns t iscpsu isc port set up time 13 15 ns t iscph isc port hold up time 10 10 ns t iscpco isc port clock to output 36 40 ns t iscpzv isc port high-impedance to valid output 36 40 ns t iscpvz isc port valid output to high-impedance 36 40 ns symbol parameter conditions -90 -12 -15 unit min max min max min max t lvdv ale access time from power-down 90 120 150 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin (pd1) 15 * t clcl 1 s symbol parameter conditions -15 -20 unit min max min max t lvdv ale access time from power-down 150 200 ns t clwh maximum delay from apd enable to internal pdn valid signal using clkin (pd1) 15 * t clcl 1 s
psd813f1v 100/110 package mechanical figure 53. pqfp52 - 52-pin plastic, quad, flat package mechanical drawing note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 d1 d 1 e ne c d2 e2 l1
101/110 psd813f1v table 75. pqfp52 - 52-pin plastic, quad, flat package mechanical dimensions symb. mm inches typ. min. max. typ. min. max. a 2.35 0.093 a1 0.25 0.010 a2 2.00 1.80 2.10 0.079 0.077 0.083 b 0.22 0.38 0.009 0.015 c 0.11 0.23 0.004 0.009 d 13.20 13.15 13.25 0.520 0.518 0.522 d1 10.00 9.95 10.05 0.394 0.392 0.396 d2 7.80 ? ? 0.307 ? ? e 13.20 13.15 13.25 0.520 0.518 0.522 e1 10.00 9.95 10.05 0.394 0.392 0.396 e2 7.80 ? ? 0.307 ? ? e 0.65 ? ? 0.026 l 0.88 0.73 1.03 0.035 0.029 0.041 l1 1.60 ? ? 0.063 0 7 0 7 n52 52 nd 13 13 ne 13 13 cp 0.10 0.004
psd813f1v 102/110 figure 54. plcc52 - 52-lead plastic lead, chip carrier package mechanical drawing note: drawing is not to scale. table 76. plcc52 - 52-lead plastic lead, chip carrier package mechanical dimensions symbol mm inches typ. min. max. typ. min. max. a 4.19 4.57 0.165 0.180 a1 2.54 2.79 0.100 0.110 a2 ? 0.91 ? 0.036 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 c 0.246 0.261 0.0097 0.0103 d 19.94 20.19 0.785 0.795 d1 19.05 19.15 0.750 0.754 d2 17.53 18.54 0.690 0.730 e 19.94 20.19 0.785 0.795 e1 19.05 19.15 0.750 0.754 e2 17.53 18.54 0.690 0.730 e1.27? ?0.050? ? r 0.89 ? ? 0.035 ? ? n52 52 nd 13 13 ne 13 13 plcc-b d e1 e 1 n d1 cp b d2/e2 e b1 a1 a a2 d3/e3 m l1 l c m1
103/110 psd813f1v figure 55. tqfp64 - 64-lead thin quad flatpack, package outline note: drawing is not to scale. qfp-a nd e1 cp b e a2 a n l a1 d1 d 1 e ne c d2 e2 l1
psd813f1v 104/110 table 77. tqfp64 - 64-lead thin quad flatpack, package mechanical data symb. mm inches typ. min. max. typ. min. max. a 1.42 1.54 0.056 0.061 a1 0.10 0.07 0.14 0.004 0.003 0.005 a2 1.40 1.36 1.44 0.055 0.054 0.057 3.5 0.0 7.0 3.5 0.0 7.0 b 0.35 0.33 0.38 0.014 0.013 0.015 c 0.17 0.006 d 16.00 15.90 16.10 0.630 0.626 0.634 d1 14.00 13.98 14.03 0.551 0.550 0.552 d2 12.00 11.95 12.05 0.472 0.470 0.474 e 16.00 15.90 16.10 0.630 0.626 0.634 e1 14.00 13.98 14.03 0.551 0.550 0.552 e2 12.00 11.95 12.05 0.472 0.470 0.474 e 0.80 0.75 0.85 0.031 0.030 0.033 l 0.60 0.45 0.75 0.024 0.018 0.030 l1 1.00 0.94 1.06 0.039 0.037 0.042 cp 0.10 0.004 n64 64 nd 16 16 ne 16 16
105/110 psd813f1v part numbering table 78. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: psd8 1 3 f 1 a ? 15 j 1 t device type psd8 = 8-bit psd with register logic sram capacity 1 = 16 kbit flash memory capacity 3 = 1 mbit (128kb x 8) 2nd flash memory 1 = 256 kbit eeprom operating voltage v = v cc = 3.0 to 3.6v speed 70 = 70ns 90 = 90ns 12 = 120ns package j = plcc52 m = pqfp52 u = tqfp64 temperature range blank = 0 to 70c (commercial) i = ?40 to 85c (industrial) option t = tape & reel packing
psd813f1v 106/110 appendix a. pqfp52 pin assignments table 79. pqfp52 connections (figure 2 ) pin number pin assignments 1pd2 2pd1 3pd0 4pc7 5pc6 6pc5 7pc4 8 v cc 9gnd 10 pc3 11 pc2 12 pc1 13 pc0 14 pa7 15 pa6 16 pa5 17 pa4 18 pa3 19 gnd 20 pa2 21 pa1 22 pa0 23 ad0 24 ad1 25 ad2 26 ad3 pin number pin assignments 27 ad4 28 ad5 29 ad6 30 ad7 31 v cc 32 ad8 33 ad9 34 ad10 35 ad11 36 ad12 37 ad13 38 ad14 39 ad15 40 cntl0 41 reset 42 cntl2 43 cntl1 44 pb7 45 pb6 46 gnd 47 pb5 48 pb4 49 pb3 50 pb2 51 pb1 52 pb0
107/110 psd813f1v appendix b. plcc52 pin assignments table 80. plcc52 connections (figure 3 ) pin number pin assignments 1gnd 2pb5 3pb4 4pb3 5pb2 6pb1 7pb0 8pd2 9pd1 10 pd0 11 pc7 12 pc6 13 pc5 14 pc4 15 v cc 16 gnd 17 pc3 18 pc2 (v stby ) 19 pc1 20 pc0 21 pa7 22 pa6 23 pa5 24 pa4 25 pa3 26 gnd pin number pin assignments 27 pa2 28 pa1 29 pa0 30 ad0 31 ad1 32 ad2 33 ad3 34 ad4 35 ad5 36 ad6 37 ad7 38 v cc 39 ad8 40 ad9 41 ad10 42 ad11 43 ad12 44 ad13 45 ad14 46 ad15 47 cntl0 48 reset 49 cntl2 50 cntl1 51 pb7 52 pb6
psd813f1v 108/110 appendix c. tqfp64 pin assignments table 81. tqfp64 connections (figure 4 ) pin number pin assignments 1pd2 2pd1 3pd0 4pc7 5pc6 6pc5 7 v cc 8 v cc 9 v cc 10 gnd 11 gnd 12 pc3 13 pc2 14 pc1 15 pc0 16 nc 17 nc 18 nc 19 pa7 20 pa6 21 pa5 22 pa4 23 pa3 24 gnd 25 gnd 26 pa2 27 pa1 28 pa0 29 ad0 30 ad1 31 n/d 32 ad2 pin number pin assignments 33 ad3 34 ad4 35 ad5 36 ad6 37 ad7 38 v cc 39 v cc 40 ad8 41 ad9 42 ad10 43 ad11 44 ad12 45 ad13 46 ad14 47 ad15 48 cntl0 49 nc 50 reset 51 cntl2 52 cntl1 53 pb7 54 pb6 55 gnd 56 gnd 57 pb5 58 pb4 59 pb3 60 pb2 61 pb1 62 pb0 63 nc 64 nc
109/110 psd813f1v revision history table 82. document revision history date rev. description of revision august-2000 1.0 document written in wsi format. 04-jan-03 1.1 front page, and back two pages, in st format, added to the pdf file. references to waferscale, wsi, easyflash and psdsoft 2000 updated to st, st, flash+psd and psdsoft express. 06-dec-03 2.0 document converted to st format. package references corrected (figure 1 ). 3-jun-04 3.0 document reformatted for dms; ordering information corrected (table 78 ); added tqfp64 package (figure 1 , 55 ; table 77 )
psd813f1v 110/110 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nseq u of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is g by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are s to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts a authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro n the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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